OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /System09/trunk/rtl/Spartan3
    from Rev 118 to Rev 126
    ↔ Reverse comparison
  •

Rev 118 → Rev 126

/sys09bug_s3s_rom4k_b16.vhd
0,0 → 1,270
--===========================================================================--
-- --
-- sys09bug_s3s_rom4k_b16.vhd - Synthesizable Sys09bug 4KB monitor ROM --
-- --
--===========================================================================--
--
-- File name : sys09bug_s3s_rom4k_b16.vhd
--
-- Purpose : Implements two Xilinx RAMB16_S9 Block RAMs as one monitor ROM
-- initialized with a 4KByte version of the Sys09bug monitor program
-- for the System09 SoC. Sys09bug is based on the SBUG1.8 ROM
-- for the old SWTPc 6809 however it has been adapted to make use
-- of the features found on the Digilent Spartan 3 Starter board.
-- It includes drivers for a VGA VDU, PS/2 keyboard and serial port
-- and allows the user to examine and modify memory and load programs
-- over the serial port.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
--
-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Copyright (C) 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 1.0 2006-11-21 John Kent Initial version (2KBytes)
-- Resides at memory location $F800 to $FFFF in System09
--
-- 1.1 2006-12-22 John Kent Made into 4K ROM/RAM.
-- Resides at memory location $F000 to $FFFF in System09
--
-- 1.2 2010-06-17 John Kent Updated header, description and GPL
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
 
begin
 
ROM0 : RAMB16_S9
generic map (
INIT_00 => x"3FF13FF13FF141F119F152F052F052F03FF13FF13FF13FF13FF141F119F1BDF7",
INIT_01 => x"7AF152F052F052F052F052F052F052F052F052F052F052F052F052F03FF13FF1",
INIT_02 => x"6E34DE9F6E32DE9F6E39FE1C5D5F52F052F052F04EF24EF24EF24EF249F2E9F1",
INIT_03 => x"0FC630350826FF8185A62ADE8E1EDEF703E6303438DE9F6E390127078D36DE9F",
INIT_04 => x"6E3ADE9F6E3035F9265AA0A780A614C632DE8E108B3002F08E3D14C639011A5D",
INIT_05 => x"6E39EA2604814C1EDEB640DE9FAD0425BC8D1BDE8E1EDEB74F3EDE9F6E3CDE9F",
INIT_06 => x"F084C5AB1FDEB62EDECEC5E61EDEF62ADECE501A22DEB7A81F44DE9F6E42DE9F",
INIT_07 => x"B70F88008639031F5F008B0F841FDEB6F0FFB7E0AB0F840F88018020DEB6E2A7",
INIT_08 => x"FF17EAFF17703439011A5D40C639041AFE1C20DEF71FDEB7398A1F22DEB6F0FF",
INIT_09 => x"5FF0355FF9265A80A7A0A65F46DE8E10CBFF17F9265AA0A7C0A65F46DE8E10A6",
INIT_0a => x"80A65F46DE8E10BAFF16032700C1072701C1C5E61EDEF62ADECEC2FF17703439",
INIT_0b => x"DE7F02340434F0355F84FF17F9265AC0A7A0A65F46DE8E105FFF17F9265AA0A7",
INIT_0c => x"2485F2BD02353D2485F2BD0235442485F2BD1EDEB64C2485F2BD738622DE7F21",
INIT_0d => x"F2BD02341B2467F2BDEB265A21DE7C032422DEB722DEBB80A7302467F2BD5F36",
INIT_0e => x"85F2BD1586092010C60D205F032485F2BD06860E2621DEB3100235891F142467",
INIT_0f => x"85F2BD1EDEB6DD2485F2BD728622DE7F21DE7F02340434395D21DEF709C6F524",
INIT_10 => x"032422DEB722DEBBBF2485F2BD80A65FC72485F2BD0235CE2485F2BD0235D524",
INIT_11 => x"5F032606819C2467F2BDA12485F2BD22DEB6A92485F2BD21DEB6EB265A21DE7C",
INIT_12 => x"205F03260681072467F2BD0C2485F2BD5186395D21DEF6395D21DEF70AC60220",
INIT_13 => x"B035EE261F30F6263F310A254700E0B6E2048E10E8038E3034395D011A10C604",
INIT_14 => x"35ED261F30F5263F310C25474700E0B6E2048E10E8038E02343034B03501E0B6",
INIT_15 => x"2E2E2E6B7369644D415220676E6974616D726F460D0AB03501E0B70235B03502",
INIT_16 => x"AAF28E04202164657461636F6C6C6120746F6E206B7369646D6152040D0A0420",
INIT_17 => x"BD1BDE8E1EDEF7396AF4BDC2F28EF52604C15C0C27018185A65F2ADE8E6AF4BD",
INIT_18 => x"4C20DEB684A71FDEB646DE8E20DEB701861FDE7FFB265A80A75F4F46DE8E6CF0",
INIT_19 => x"B70186D7260F8120DEB620DE7C5BF0BD20DEF61FDEB601A70186846C04260F81",
INIT_1a => x"C6BF86016F846F46DE8E57F0BD0EC6BF8646DE8EC826C0811FDEB61FDE7C20DE",
INIT_1b => x"03C64F46DE8E5BF0BD0EC64F016F846F46DE8E57F0BD0EC64F46DE8E5BF0BD0E",
INIT_1c => x"ED204BCC1488ED5349CC1288ED444DCC1088ED4152CC016F846F46DE8E57F0BD",
INIT_1d => x"01862188ED720ACC2688ED1F88ED0EC6BF861D88ED0101CC1B88ED0100CC1688",
INIT_1e => x"8646DE8E57F0BD01C64F46DE8E5BF0BD03C64F2588A707862488A707862388A7",
INIT_1f => x"206C616E7265746E6920676E69746F6F4208085BF07E01C64F01A7558684A7AA",
INIT_20 => x"26FDD38C81EDA1EC34F48E10E5D38E6AF4BDEDF38E040A0D2E2E2E2E58454C46",
INIT_21 => x"82F482F4C8DFC2DF82F476F400CD7EF7261EDE8C81EDA1EC4CF48E1000DE8EF7",
INIT_22 => x"F07E9FF07E6CF07E63F07E5FF07E5BF07E57F07E72F46EF47AF482F47EF482F4",
INIT_23 => x"9F6E08F89F6E04F89F6E06F89F6E0AF89F6E0CF89F6EC3F07EBFF07EA7F07EA3",
INIT_24 => x"040A0D2E2E2E2064616F6C7075206B736944204D4F52206C61697265533900F8",
INIT_25 => x"01C64F1EDEB700866AF4BD83F48E040A0D646564616F4C206B736944204D4F52",
INIT_26 => x"E0260FC15C20DEF61FDEB626FC17F8265AC0A7EDF4BD5FFEFB1720DEF71FDEB7",
INIT_27 => x"BD8435E0AB0434068D891F484848480E8D04346AF47EA0F48ED92630814C01C6",
INIT_28 => x"B7038639018500E0B6390780EB2E1681EF2B11810A2F0981F72B3080FB2928F5",
INIT_29 => x"DD8D0A2778850826018500E0B629DE7F28DE7F27DEB710863900E0B7118600E0",
INIT_2a => x"00E0B6023439021A4FDC2627DE7AE12628DE7AE62629DE7A39021C01E0B6E620",
INIT_2b => x"44204D4F52206D65646F6D580A0D3901E0B70235F120B38DF527788508260285",
INIT_2c => x"550A0D046574656C706D6F432064616F6C70550A0D0464616F6C7055206B7369",
INIT_2d => x"B7008625DEBF1AF68E23DEB70186B8FE1772F58E04726F7272452064616F6C70",
INIT_2e => x"F61FDEB61FFB17F6265AC0A720252B00175FF9FA1720DEF71FDEB701C64F1EDE",
INIT_2f => x"BE10346DFE169DF58E04FB176AF47E8BF58ED72630814C01C6DE260FC15C20DE",
INIT_30 => x"F68E06260181903525DEBFED2684ADF1201AF68E4FFF1715860A2823FF1725DE",
INIT_31 => x"8E062623DEB139FA1C39051A0326188139051A2EFF1706860826048139FA1C3A",
INIT_32 => x"F68E24DEB7808621DE7FEF2623DEB14339FA1C1AF68E11FF17158639FA1C50F6",
INIT_33 => x"072621DEB139041AFE1C7BF68E032624DE7A023521DEB721DEBB023439FA1C64",
INIT_34 => x"4C080839FA1C1AF68EC4FE1715860435031F80C45A301F04340D20068623DE7C",
INIT_35 => x"46042E4D4F5250206769666E6F63206D6F7266206B736964204D4F522064616F",
INIT_36 => x"4D4F52040D0A2E2E2E6174616420676E6964616F6C202C434E595320646E756F",
INIT_37 => x"756F4620746F4E206B736944204D4F52040D0A2E646564616F4C206B73694420",
INIT_38 => x"00008C1F3015277C8D6C8D00008E20008E105A8D6AF4BD9DF68E040D0A2E646E",
INIT_39 => x"F71FDEB701C61EDEB74F6AF4BDBFF68E6AF47EF0F68EEB2600008C101F31F326",
INIT_3a => x"30814C01C6E1260FC15C20DEF61FDEB6ABF917F9265AC0A7678D5F82F91720DE",
INIT_3b => x"BF46DFBFF92600008C1F3000008EC0E0B70086C0E0B702866AF47EDDF68EDA26",
INIT_3c => x"FFCC46DF7947DF7948DF793949DF7844C0E0B6C0E0B70086C0E0B701863948DF",
INIT_3d => x"B2FC17843549DFB6FB265ACE8D08C604343946DFB31055AACC072648DFB31000",
INIT_3e => x"F4F78EF526F4F78C02300D2780E1E5F78E20C0022F60C1A5FC172086891F7F84",
INIT_3f => x"000000040D0A3F2054414857ACF55806F750DDF246B2F44C0BF442946E87FC16"
)
 
port map (
do => rdata0,
dop(0) => dp0,
addr => addr(10 downto 0),
clk => clk,
di => wdata,
dip(0) => dp0,
en => cs0,
ssr => rst,
we => we
);
 
ROM1 : RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E1074FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"0317A8FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031784FE8E9F04",
INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B30217AFFE8E2E",
INIT_04 => x"20F00217B1FE8EF52674FE8C02300F2780E13BFE8E20C0022F60C14704174C04",
INIT_05 => x"17A4A60F0417A50317211F650217B7FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117B7FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7",
INIT_10 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E3",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4ECF901171286E3FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017F8FE8E64E720C602",
INIT_18 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016A101169035690017A9FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DBBFE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DCDFE8EE12044AED78DD3FE8EB4001643A6E18DD9FE8EF42048AEEA8DC7FE8E",
INIT_1e => x"D02042A6B38DE4FE8ED92041A6BC8DDFFE8ECF204AAEC58DC1FE8ED82046AECE",
INIT_1f => x"B7FE8EBF8DB88DB08DA98DA18D27FF17B7FE8E900016F0FE8EC4A6AA8DE9FE8E",
INIT_20 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
INIT_25 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
INIT_26 => x"3501A70235FA27028584A6E0DFBE1234458D2086008D8235018520E0B6052601",
INIT_27 => x"A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A7118684A70386E0DFBE138D90",
INIT_28 => x"8D0427FEDF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702",
INIT_29 => x"1A816C0027101B814100271008819635C5001784A70520098D042420810D2074",
INIT_2a => x"51260A81110027100B812C0027100C81990027100D814500271016818E002710",
INIT_2b => x"164A3327FBDFB67400165A3C0027105DFBDFFC9900168300261019C15CFBDFFC",
INIT_2c => x"2710598116273DC1FEDFF65800160000CC5B00162500271050814CFBDFB66800",
INIT_2d => x"2080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D81312754816E00",
INIT_2e => x"A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6ED224F81",
INIT_2f => x"C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF726508102",
INIT_30 => x"2650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D5AEA2619",
INIT_31 => x"FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15CFCDFF6F4",
INIT_32 => x"505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB047FFB0369",
INIT_33 => x"94F9A7F8A7F8A7F8A7F894F992FC55D5F94488F958F1F853EDFB52A8F84DBCFA",
INIT_34 => x"52415453335320524F4620342E312047554239305359530000000A0DFFFFFFFF",
INIT_35 => x"3D5053202004202D20043F54414857043E040000000A0D4B04202D2020524554",
INIT_36 => x"20043D50442020043D58492020043D59492020043D53552020043D4350202004",
INIT_37 => x"000000000004315343565A4E4948464504203A43432020043D422020043D4120",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
 
port map (
do => rdata1,
dop(0) => dp1,
addr => addr(10 downto 0),
clk => clk,
di => wdata,
dip(0) => dp1,
en => cs1,
ssr => rst,
we => we
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/sys09s3e.vhd
0,0 → 1,101
--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
-- made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
component SYS09BUG_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : SYS09BUG_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata0
);
 
addr_f800 : SYS09BUG_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata1
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/sys09s3s_b4.vhd
0,0 → 1,362
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E1062FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"031796FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031772FE8EA304",
INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B302179DFE8E2E",
INIT_04 => x"20F002179FFE8EF52662FE8C02300F2780E129FE8E20C0022F60C14704174C04",
INIT_05 => x"17A4A60F0417A50317211F650217A5FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117A5FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E7",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4ECF901171286E7FCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017E6FE8E64E720C602",
INIT_08 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016A10116903569001797FE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DA9FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DBBFE8EE12044AED78DC1FE8EB4001643A6E18DC7FE8EF42048AEEA8DB5FE8E",
INIT_0e => x"D02042A6B38DD2FE8ED92041A6BC8DCDFE8ECF204AAEC58DAFFE8ED82046AECE",
INIT_0f => x"A5FE8EBF8DB88DB08DA98DA18D27FF17A5FE8E900016DEFE8EC4A6AA8DD7FE8E"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
INIT_05 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
INIT_06 => x"35F6260885FA27028584A6E0DFBE1234498D2086008D8235018520E0B6052601",
INIT_07 => x"0000CC30E08E39E2DFB7FF86016D84A7518684A70386E0DFBE138D903501A702",
INIT_08 => x"DF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702A7FBDFFD",
INIT_09 => x"1A815A271B81342708819635AF001784A70520098D042420810D20608D0427FE",
INIT_0a => x"19C15CFBDFFC45260A810F270B8124270C81890027100D81382716817C002710",
INIT_0b => x"5820212750814CFBDFB662204A2C27FBDFB66D205A34275DFBDFFC8F00167926",
INIT_0c => x"39FEDF7F39FEDFB704263D81312754816E27598114273DC1FEDFF656200000CC",
INIT_0d => x"1B20E12218C120C0FDDF7FFDDFF6ED224F812080FEDF7F39FDDFB70426FDDF7D",
INIT_0e => x"02A7FBDFFDFCDFF64F39FEDF7FF726508102A74C84E720C6FBDFB6168D0000CC",
INIT_0f => x"DFF604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CFBDFFC3903E7"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"5FE4205F03E7FCDFF7082719C15CFCDFF6F42650C15C84A702E7FBDFF72086FB",
INIT_01 => x"FB1953FB183DFB1531FB105EFB047FFB0369FB0274FB0139FEDFF702E7FBDFF7",
INIT_02 => x"55D5F94488F958F1F853EDFB52A8F84DBCFA505EFA4CA5F847FDF8455CF94248",
INIT_03 => x"2047554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F992FC",
INIT_04 => x"57043E040000000A0D4B04202D202052455452415453335320524F4620362E31",
INIT_05 => x"3D59492020043D53552020043D43502020043D5053202004202D20043F544148",
INIT_06 => x"464504203A43432020043D422020043D412020043D50442020043D5849202004",
INIT_07 => x"000000000000000000000000000000000000000000000004315343565A4E4948",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
/sys09xes.vhd
0,0 → 1,101
--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
-- made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal rdata0 : std_logic_vector(7 downto 0);
signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
component SYS09BUG_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : SYS09BUG_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata0
);
 
addr_f800 : SYS09BUG_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
rw => rw,
addr => addr(10 downto 0),
wdata => wdata,
rdata => rdata1
);
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
we <= not rw;
case addr(11) is
when '0' =>
cs0 <= cs;
cs1 <= '0';
rdata <= rdata0;
when '1' =>
cs0 <= '0';
cs1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/sys09xes_b16.vhd
0,0 → 1,294
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"8C02300D2780E12CF08E20C0022F60C10AF89FAD2086891F7F8406F89FAD02F0",
INIT_01 => x"CD8E040D0A3F2054414857BCF258EAF0463EF042946E29021635F08EF52635F0",
INIT_02 => x"B6B035EE261F30F6263F310A254700E0B6E2048E10E8038E30343B341F4AAF00",
INIT_03 => x"0235ED261F30F5263F310C25474700E0B6E2048E10E8038E02343034B03501E0",
INIT_04 => x"2E2E2E6B7369642045444920676E6974616D726F460D0AB03501E0B70235B035",
INIT_05 => x"6E20657669726420454449040D0A043F207265626D754E2065766972440D0A20",
INIT_06 => x"6574656C706D6F432074616D726F460D0A04202164657461636F6C6C6120746F",
INIT_07 => x"002510308169FF17FB2450FF1753F2BD89F08EBDF4BD04204B53494445444904",
INIT_08 => x"017FFB265A80A75F4F00028E3AF5BDFD008E0001F7891F3080E90022103381EF",
INIT_09 => x"F60101B601A70186846C042600814C0201B684A70101B600028E0201B7018601",
INIT_0a => x"028EC82600810101B601017C0201B70186D72600810201B602017C15F5BD0201",
INIT_0b => x"8EF1F4BDFFC64F00028E15F5BDFFC6FF86016F846F00028EF1F4BDFFC6FF8600",
INIT_0c => x"8E102034016F846F00028EF1F4BD03C64F00028E15F5BDFFC64F016F846F0002",
INIT_0d => x"FFC6FF861D88ED0101CC1B88ED0001F64F2035F72618C15C85A7A0A610C6E1F0",
INIT_0e => x"F5BD03C64F2588A707862488A707862388A701862188ED01FECC2688ED1F88ED",
INIT_0f => x"E0B7038639018500E0B653F27ECFF08E2503170201F70101B701C64F00F78E15",
INIT_10 => x"20DD8D0A2778850826018500E0B60A017F09017F0801B710863900E0B7118600",
INIT_11 => x"8500E0B6023439021A4FDC2608017AE12609017AE6260A017A39FD1C01E0B6E6",
INIT_12 => x"646F6D580A0D39F826048180A6E78D3901E0B70235F120B38DF5277885082602",
INIT_13 => x"706D6F432064616F6C70550A0D0464616F6C7055206B73694420454449206D65",
INIT_14 => x"626D754E2065766972440A0D04726F7272452064616F6C70550A0D046574656C",
INIT_15 => x"175AF28E04294E2F5928203F206572755320756F59206572410A0D043A207265",
INIT_16 => x"01B730802801221033812E01251030816AFF17FB293CFF178BFF1794F28E91FF",
INIT_17 => x"815F843DFF17FB290FFF175EFF17A5F28E4BFF17308B0001B66CFF1794F28E00",
INIT_18 => x"0101B701C64F00028E0401B701860601FF2DF4CEB10117B3265981FF0027104E",
INIT_19 => x"D501170201F60101B600028ED6002510E00017870117E0002510EA00170201F7",
INIT_1a => x"B00017570117B0002510BA00170201F70101B75C0201F60101B600028E710117",
INIT_1b => x"0101B75C0201F60101B600028E410117A501170201F60101B600028EA6002510",
INIT_1c => x"88E60B01B74C2688A600028E76002510800017270117800025108A00170201F7",
INIT_1d => x"01F70101B700028E5C0201F60101B60301176701170201F60101B60C01F75C27",
INIT_1e => x"00173701170201F60101B600028E38002510420017E90017420025104C001702",
INIT_1f => x"01F70101B701C64F00F78EC3260B01B14C01C6CB260C01F15C0201F60101B6D3",
INIT_20 => x"CE1BFE1715860A28EFFD170601FE403443FE1685F28E53F27E73F28E11011702",
INIT_21 => x"FAFD1706860826048139FA1C4DF4CE06260181C0350601FFED26C4ADF1202DF4",
INIT_22 => x"2DF4CEDDFD17158639FA1C63F4CE06260401B139FA1C39051A0326188139051A",
INIT_23 => x"350301B70301BB023439FA1C77F4CE0501B7808603017FEF260401B14339FA1C",
INIT_24 => x"043439041AFE1C2DF4CE04017C0B260301B139FA1C80A78EF4CE032605017A02",
INIT_25 => x"0600CC82357FFD170686023439FA1C2DF4CE8CFD1715860435011F80C45A101F",
INIT_26 => x"E4E606E1FD5A4F023401C64F668DD602160CE1FDE000CC1EE1FD0200CC1EE1FD",
INIT_27 => x"8E102034AC02170EE1FD2000CCE48D82355F04E1FD01C60AE1FD0001F608E1FD",
INIT_28 => x"8802170EE1FD3000CCC08D395F9502172035F4263F3180E700E1FCB202170001",
INIT_29 => x"0123038103A6395F7002172035F4263F3100E1FD80E68D02174F00018E102034",
INIT_2a => x"00000000000000000000000000000000000000000000395F03A6395F0001B74F",
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"270281358D00C48E1000C3FDF18CECFFC0CE1000000000C00000000000000B20",
INIT_39 => x"5D891F158DD08CA71A8DD48CA71F8DEA20DA8CA7268DDE8CA72B8DF626168110",
INIT_3a => x"8D0B2784EC00C38E0F2600C48C10C920F5265A80A71435098D1434C58CAED927",
INIT_3b => x"C60AE1FD908CE608E1FDE4E606E1FD5A4F02349B9C6E39A0A604C38E109D2626",
INIT_3c => x"3F3180E700E1FC1E8D00018E102034178D0EE1FD2000CCE48D82355F04E1FD01",
INIT_3d => x"0039F92708C50EE1FC39F22740C50EE1FCF92680C50EE1FC395F028D2035F526",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => wdata,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
rdata <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E1074FE8E2EFA1AFB1EFB8FFBE0FCC5FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"0317A3FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031784FE8EB504",
INIT_03 => x"17408B981F6504175E86092C2081891FF1270D817F84370417B30217AAFE8E2E",
INIT_04 => x"20F00217ACFE8EF52674FE8C02300F2780E13BFE8E20C0022F60C15904175E04",
INIT_05 => x"17A4A6210417A50317211F650217B2FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317190417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F703173F86FA031708",
INIT_08 => x"27A603170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265AA003172C031780A610C6A803172E0317E4AEEE0117B2FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8903172E8602237E810425208180A610C6E1AE980317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105803163F865B0317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E",
INIT_10 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F7A02171186F9",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F2402161386E2DF732C02173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4EC0B02171286F9FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017F3FE8E64E720C602",
INIT_18 => x"10347120028D396532C901171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016B301169035690017A4FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DB6FE8E39F726048180A651011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DC8FE8EE12044AED78DCEFE8EB4001643A6E18DD4FE8EF42048AEEA8DC2FE8E",
INIT_1e => x"D02042A6B38DDFFE8ED92041A6BC8DDAFE8ECF204AAEC58DBCFE8ED82046AECE",
INIT_1f => x"B2FE8EBF8DB88DB08DA98DA18D27FF17B2FE8E900016EBFE8EC4A6AA8DE4FE8E",
INIT_20 => x"3C29088D011F42290E8DCA00172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602346320078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"207F84048D0627E2DF7D00F09F6E8235F1265A518D558D2D860225E46880A608",
INIT_25 => x"DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA7118610343F",
INIT_26 => x"2086008D8235018520E0B605260185E0DF9FA6E0DF9FA711860234903501A6E0",
INIT_27 => x"84A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE1234498D",
INIT_28 => x"02C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A75186",
INIT_29 => x"20098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FEDF7F01E7",
INIT_2a => x"890027100D81382716817C0027101A815A271B81342708819635AF001784A705",
INIT_2b => x"6D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B8124270C81",
INIT_2c => x"598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C27FBDFB6",
INIT_2d => x"2080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D81312754816E27",
INIT_2e => x"A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6ED224F81",
INIT_2f => x"C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF726508102",
INIT_30 => x"2650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D5AEA2619",
INIT_31 => x"FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15CFCDFF6F4",
INIT_32 => x"505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB047FFB0369",
INIT_33 => x"94F9A7F8A7F8A7F8A7F894F992FC55D5F94488F958F1F853EDFB52A8F84DBCFA",
INIT_34 => x"20205353455820524F4620362E312047554239305359530000000A0DFFFFFFFF",
INIT_35 => x"43502020043D5053202004202D20043F54414857043E040000000A0D4B04202D",
INIT_36 => x"20043D412020043D50442020043D58492020043D59492020043D53552020043D",
INIT_37 => x"0000000000000000000004315343565A4E4948464504203A43432020043D4220",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => wdata,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
rdata <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
/sys09s3s.vhd
0,0 → 1,151
--===========================================================================--
-- --
-- Synthesizable 4K Sys09_bug ROM using Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : sys09s3s_b16.vhd
--
-- Entity name : mon_rom
--
-- Purpose : Implements a 4KByte Sys09_bug ROM
-- for the 200K gate Digilent spartan 3 starter board
-- using two Xilinx RAMB16_S9 Block RAM
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : SYS09BUG_F000
-- SYS09BUG_F800
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Block RAM instatiation
--
-- Copyright (C) 2006 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 1.0 2006-11-21 John Kent Initial version
-- 1.1 2006-12-22 John Kent Made into 4K ROM/RAM.
-- 1.2 2010-06-17 John Kent Added GPL and header
-- Renamed data input and output signals
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (11 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal data_out0 : std_logic_vector(7 downto 0);
signal data_out1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
 
component SYS09BUG_F800
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
 
begin
 
addr_f000 : SYS09BUG_F000 port map (
clk => clk,
rst => rst,
cs => cs0,
addr => addr(10 downto 0),
rw => rw,
data_in => data_in,
data_out => data_out0
);
 
addr_f800 : SYS09BUG_F800 port map (
clk => clk,
rst => rst,
cs => cs1,
addr => addr(10 downto 0),
rw => rw,
data_in => data_in,
data_out => data_out1
);
 
my_mon : process ( rw, addr, cs, data_out0, data_out1 )
begin
we <= not rw;
cs0 <= '0';
cs1 <= '0';
case addr(11) is
when '0' =>
cs0 <= cs;
data_out <= data_out0;
when '1' =>
cs1 <= cs;
data_out <= data_out1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/sys09s3e_b4.vhd
0,0 → 1,362
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C07F8E104EFE8ECFFE0DFB11FB82FBBDFCA8FC8AFC90FC4BF814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6450117D07FBF00E08EF9265AA0",
INIT_02 => x"092C2081891FF1270D817F843C0417BC021783FE8EDE01173A03175EFE8E9204",
INIT_03 => x"FE8C02300F2780E118FE8E20C0022F60C14C0417510417408B981F5804175E86",
INIT_04 => x"1F6E02178BFE8E121F2D297403173B341FBC2094ADC020F9021785FE8EF5264E",
INIT_05 => x"17275E81DD271881E127088111286703170C0417AE0317A4A6140417AE031721",
INIT_06 => x"321FAB0217BE203F31C2202131EA03173F86ED03170827A4A1A4A7390F260D81",
INIT_07 => x"F0C4201F0634F0C41000C3101F390124E1AC2034062914031705201F30C07F8E",
INIT_08 => x"10C69B0317370317E4AEF701178BFE8E103439623203279F03170527E4AC011F",
INIT_09 => x"03172E8602237E810425208180A610C6E1AE8B0317F5265A93031735031780A6",
INIT_0a => x"273F8184A60F2710355B8DFFFF8E10341A24C07F8C1E29C00217BC20EE265A7C",
INIT_0b => x"431F39FB265A1E8D08C6D37F8E104B03163F864E03173984A73F86A4AFA0A709",
INIT_0c => x"A60A24C07F8C21AEB3FE16ED7FBF00008E5102170C8D4AAF04272C8D1F304AAE",
INIT_0d => x"265A0427A1ACA0A608C6D37F8E1039A0A7A0A7A0A7FF8684A7A4A604263F8184",
INIT_0e => x"7FBFE7F98EEB7FBFC07FBEED7FBF1429390217EE02171C295F0117393D3139F7",
INIT_0f => x"27ED7FBE24273F8184A64AAEEC011770E0B671E0B73686431F392020450017C0"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"3B71E0B73F8673E0B7368670E0B671E0B7368670E0B70D86341FED7FBF1F301F",
INIT_01 => x"B7368672E0B7008670E0B7FF8673E0B73A8671E0B7328622FE16C07FBFEB7FBE",
INIT_02 => x"81260217D27F7F6402171186D6FCBD8435FD265A20C604343973E0B73E8671E0",
INIT_03 => x"E0EBE0E61034212991011726290234A80117F12631813D2739811F0217F92653",
INIT_04 => x"FFC102355FEB2080A70527E46AE0EB02340C2904358E01170434E46AE46AE4EB",
INIT_05 => x"E4AF0130492562AC4D2930344A0117E26F0E02161386D27F731602173F86BA27",
INIT_06 => x"03CB2F0017CCFE8E64E720C6022320008310062762A3E4ECF501171286D6FCBD",
INIT_07 => x"AF5B0117981F53F526646A65011780A684EB63EB62EB68011762AE750117981F",
INIT_08 => x"00169D011690356900177DFE8E10347120028D396532B301171486C326E4AC62",
INIT_09 => x"8DDC8D728D3948AF0229EB8DE78D618D394AAF0229F68DF28D910017E50016F8",
INIT_0a => x"BB8D6C8D3943A70229C78DC68D498D3944AF0229D58DD18D5E8D3946AF0229E0",
INIT_0b => x"1739C4A7808A0429A68DA58D5F8D3941A70229B18DB08D588D3942A70229BC8D",
INIT_0c => x"8DADFE8EF42048AEEA8D9BFE8EBF0016311FF48D8FFE8E39F726048180A63B01",
INIT_0d => x"204AAEC58D95FE8ED82046AECE8DA1FE8EE12044AED78DA7FE8EB4001643A6E1",
INIT_0e => x"900016C4FE8EC4A6AA8DBDFE8ED02042A6B38DB8FE8ED92041A6BC8DB3FE8ECF",
INIT_0f => x"098DD520CE8DC78DC08D17FF178BFE8EBF8DB88DB08DA98DA18D27FF178BFE8E"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"4848483229118D903561A710343C29088D011F42290E8DB400172D86121F4D29",
INIT_01 => x"22468112254181393080032239811D253081578D39E0AB04342829078D891F48",
INIT_02 => x"4444444402340235028D0235103439021A395780032266810725618139378003",
INIT_03 => x"3B8D3F8D2D860225E46880A608C602344D20078B022F3981308B0F840235048D",
INIT_04 => x"84A620E08E0926018584A6D07FBE10342D207F84048D0627D27F7D8235F1265A",
INIT_05 => x"34498D2086008D8235018520E0B605260185D07F9FA60234903501A6EE270185",
INIT_06 => x"A7518684A70386D07FBE138D903501A70235F6260885FA27028584A6D07FBE12",
INIT_07 => x"7F01E702C6F17FFD04E703E702A7EF7FFD0000CC30E08E39D27FB7FF86016D84",
INIT_08 => x"84A70520098D042420810D20608D0427F27F7D30E08E16345986028D1B86F27F",
INIT_09 => x"270C81890027100D81382716817C0027101A815A271B81342708819635AF0017",
INIT_0a => x"EF7FB66D205A34275DEF7FFC8F0016792619C15CEF7FFC45260A810F270B8124",
INIT_0b => x"816E27598114273DC1F27FF656200000CC5820212750814CEF7FB662204A2C27",
INIT_0c => x"224F812080F27F7F39F17FB70426F17F7D39F27F7F39F27FB704263D81312754",
INIT_0d => x"508102A74C84E720C6EF7FB6168D0000CC1B20E12218C120C0F17F7FF17FF6ED",
INIT_0e => x"EA2619C15C4FF02650814CEF7FFC3903E702A7EF7FFDF07FF64F39F27F7FF726",
INIT_0f => x"7FF6F42650C15C84A702E7EF7FF72086EF7FF604E75F012519C15C04E6E78D5A"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"FB035CFB0267FB0139F27FF702E7EF7FF75FE4205F03E7F07FF7082719C15CF0",
INIT_01 => x"4DAFFA5051FA4C8FF847E7F84546F9423BFB1946FB1830FB1524FB1051FB0472",
INIT_02 => x"0A0DFFFFFFFF7EF991F891F891F891F87EF9C5F95472F958DBF853E0FB5292F8",
INIT_03 => x"000A0D4B04202D202045335320524F4620362E31204755423930535953000000",
INIT_04 => x"3D53552020043D43502020043D5053202004202D20043F54414857043E040000",
INIT_05 => x"432020043D422020043D412020043D50442020043D58492020043D5949202004",
INIT_06 => x"C07F9F6E38F916D27FF7535FC07FCE103904315343565A4E4948464504203A43",
INIT_07 => x"FF8CCC7FBE49584F4AAF80E64AAE431FCA7F9F6EC87F9F6EC67F9F6EC47F9F6E",
INIT_08 => x"000000000000C27F9F6E42EE1F37F16E44AEC4EC10340822CE7FBC8B300F27FF",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"D0FEDCFEECFEE8FEE4FEE0FEF0FEDCFE00000000000000000000000000000000"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
/sys09bug_xes_rom4k_b16.vhd
0,0 → 1,281
--==========================================================================--
-- --
-- Synthesizable SYS09BUG Monitor Program for XESS XSA-3S1000 & XuLA boards --
-- --
--==========================================================================--
--
-- File name : sys09bug_xes_rom4k_b16.vhd
--
-- Entity name : mon_rom
--
-- Purpose : Implements a 4KByte Sys09bug monitor ROM for System09
-- as implemented on the XESS XSA-3S1000 & XuLA FPGA boards
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
--
-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Sys09bug monitor ROM for the XESS XSA-3S1000 and XuLA FPGA Boards
-- Resides at $F000-$FFFF
-- The lower 2KB ($F000-$F7FF) is read/writeable
-- The upper 2KB ($F800-$FFFF) is read only
-- Assumes I/O at $E000-$EFFF
-- Control ACIA at $E000-$E001
-- PS/2 keyboard at $E020-$E021
-- VDU8 at $E030-$E034
-- IDE interface at $E100-$E13F
-- Assumes RAM at $DFC0-$DFFF
--
-- Copyright (C) 2011 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 1.0 2006-11-21 John Kent Initial release
-- 1.1 2006-12-22 John Kent made into 4K ROM/RAM.
-- 1.2 2011-06-04 John Kent Updated header and description and added GPL
-- Made lower 2KB ($F000-$F7FF) read/writeable
-- Made upper 2KB ($F800-$FFFF) read only
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal we : std_logic;
signal cs0 : std_logic;
signal cs1 : std_logic;
signal dp0 : std_logic;
signal dp1 : std_logic;
signal data_out0 : std_logic_vector(7 downto 0);
signal data_out1 : std_logic_vector(7 downto 0);
 
 
begin
 
--
-- lower block is writeable
--
ROM0 : RAMB16_S9
generic map (
INIT_00 => x"8C02300D2780E12CF08E20C0022F60C10AF89FAD2086891F7F8406F89FAD02F0",
INIT_01 => x"CD8E040D0A3F2054414857B7F258E1F0463EF042946E24021635F08EF52635F0",
INIT_02 => x"B6B035EE261F30F6263F310A254700E0B6E2048E10E8038E30343B341F4AAF00",
INIT_03 => x"0235ED261F30F5263F310C25474700E0B6E2048E10E8038E02343034B03501E0",
INIT_04 => x"2E2E2E6B7369642045444920676E6974616D726F460D0AB03501E0B70235B035",
INIT_05 => x"6E20657669726420454449040D0A043F207265626D754E2065766972440D0A20",
INIT_06 => x"6574656C706D6F432074616D726F460D0A04202164657461636F6C6C6120746F",
INIT_07 => x"3080ED0022103381F3002510308172FF17FB2459FF174EF2BD89F08EB8F4BD04",
INIT_08 => x"00028E0201B7018601017FFB265A80A75F4F00028E35F5BDFD008E0001F7891F",
INIT_09 => x"B602017C10F5BD0201F60101B601A70186846C042600814C0201B684A70101B6",
INIT_0a => x"8EECF4BDFFC63F8600028EC82640810101B601017C0201B70186D72600810201",
INIT_0b => x"FFC64F016F846F00028EECF4BDFFC64F00028E10F5BDFFC63F86016F846F0002",
INIT_0c => x"CC1288ED444DCC1088ED4152CC016F846F00028EECF4BD03C64F00028E10F5BD",
INIT_0d => x"88ED1F88EDFFC63F861D88ED0101CC1B88ED0100CC1688ED204BCC1488ED5349",
INIT_0e => x"4F00F78E10F5BD03C64F2588A707862488A707862388A701862188EDC13ECC26",
INIT_0f => x"E0B7118600E0B7038639018500E0B64EF27ECFF08E2503170201F70101B701C6",
INIT_10 => x"1C01E0B6E620DD8D0A2778850826018500E0B60A017F09017F0801B710863900",
INIT_11 => x"78850826028500E0B6023439021A4FDC2608017AE12609017AE6260A017A39FD",
INIT_12 => x"4449206D65646F6D580A0D39F826048180A6E78D3901E0B70235F120B38DF527",
INIT_13 => x"046574656C706D6F432064616F6C70550A0D0464616F6C7055206B7369442045",
INIT_14 => x"043A207265626D754E2065766972440A0D04726F7272452064616F6C70550A0D",
INIT_15 => x"8FF28E91FF1755F28E04294E2F5928203F206572755320756F59206572410A0D",
INIT_16 => x"178FF28E0001B730802801221033812E01251030816AFF17FB293CFF178BFF17",
INIT_17 => x"FF0027104E815F843DFF17FB290FFF175EFF17A0F28E4BFF17308B0001B66CFF",
INIT_18 => x"00170201F70101B701C64F00028E0401B701860601FF28F4CEB10117B3265981",
INIT_19 => x"028E710117D501170201F60101B600028ED6002510E00017870117E0002510EA",
INIT_1a => x"8EA6002510B00017570117B0002510BA00170201F70101B75C0201F60101B600",
INIT_1b => x"00170201F70101B75C0201F60101B600028E410117A501170201F60101B60002",
INIT_1c => x"0C01F75C2788E60B01B74C2688A600028E76002510800017270117800025108A",
INIT_1d => x"104C00170201F70101B700028E5C0201F60101B60301176701170201F60101B6",
INIT_1e => x"F60101B6D300173701170201F60101B600028E38002510420017E90017420025",
INIT_1f => x"8E1101170201F70101B701C64F00F78EC3260B01B14C01C6CB260C01F15C0201",
INIT_20 => x"ADF12028F4CE1BFE1715860A28EFFD170601FE403443FE1680F28E4EF27E6EF2",
INIT_21 => x"188139051AFAFD1706860826048139FA1C48F4CE06260181C0350601FFED26C4",
INIT_22 => x"B14339FA1C28F4CEDDFD17158639FA1C5EF4CE06260401B139FA1C39051A0326",
INIT_23 => x"2605017A02350301B70301BB023439FA1C72F4CE0501B7808603017FEF260401",
INIT_24 => x"80C45A101F043439041AFE1C28F4CE04017C0B260301B139FA1C80A789F4CE03",
INIT_25 => x"00CC1EE1FD0600CC82357FFD170686023439FA1C28F4CE8CFD1715860435011F",
INIT_26 => x"01F608E1FDE4E606E1FD5A4F023401C64F668DDB02160CE1FDE000CC1EE1FD02",
INIT_27 => x"B7021700018E102034B102170EE1FD2000CCE48D82355F04E1FD01C60AE1FD00",
INIT_28 => x"018E1020348D02170EE1FD3000CCC08D395F9A02172035F4263F3180E700E1FC",
INIT_29 => x"5F0001B74F0123038103A6395F7502172035F4263F3100E1FD80E69202174F00",
INIT_2a => x"000000000000000000000000000000000000000000000000000000395F03A639",
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"270281358D00C48E1000C3FDF18CECFFC0CE1000000000C00000000000000B20",
INIT_39 => x"5D891F158DD08CA71A8DD48CA71F8DEA20DA8CA7268DDE8CA72B8DF626168110",
INIT_3a => x"8D0B2784EC00C38E0F2600C48C10C920F5265A80A71435098D1434C58CAED927",
INIT_3b => x"C60AE1FD908CE608E1FDE4E606E1FD5A4F02349B9C6E39A0A604C38E109D2626",
INIT_3c => x"3F3180E700E1FC1E8D00018E102034178D0EE1FD2000CCE48D82355F04E1FD01",
INIT_3d => x"0039F92708C50EE1FC39F22740C50EE1FCF92680C50EE1FC395F028D2035F526",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map (
do => data_out0,
dop(0) => dp0,
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp0,
en => cs0,
ssr => rst,
we => we
);
 
--
-- upper block is not writeable
--
ROM1 : RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E1074FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"0317A3FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031784FE8E9F04",
INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B30217AAFE8E2E",
INIT_04 => x"20F00217ACFE8EF52674FE8C02300F2780E13BFE8E20C0022F60C14704174C04",
INIT_05 => x"17A4A60F0417A50317211F650217B2FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117B2FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E",
INIT_10 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E3",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4ECF901171286E3FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017F3FE8E64E720C602",
INIT_18 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016A101169035690017A4FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DB6FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DC8FE8EE12044AED78DCEFE8EB4001643A6E18DD4FE8EF42048AEEA8DC2FE8E",
INIT_1e => x"D02042A6B38DDFFE8ED92041A6BC8DDAFE8ECF204AAEC58DBCFE8ED82046AECE",
INIT_1f => x"B2FE8EBF8DB88DB08DA98DA18D27FF17B2FE8E900016EBFE8EC4A6AA8DE4FE8E",
INIT_20 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
INIT_25 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
INIT_26 => x"3501A70235FA27028584A6E0DFBE1234458D2086008D8235018520E0B6052601",
INIT_27 => x"A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A7118684A70386E0DFBE138D90",
INIT_28 => x"8D0427FEDF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702",
INIT_29 => x"1A816C0027101B814100271008819635C5001784A70520098D042420810D2074",
INIT_2a => x"51260A81110027100B812C0027100C81990027100D814500271016818E002710",
INIT_2b => x"164A3327FBDFB67400165A3C0027105DFBDFFC9900168300261019C15CFBDFFC",
INIT_2c => x"2710598116273DC1FEDFF65800160000CC5B00162500271050814CFBDFB66800",
INIT_2d => x"2080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D81312754816E00",
INIT_2e => x"A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6ED224F81",
INIT_2f => x"C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF726508102",
INIT_30 => x"2650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D5AEA2619",
INIT_31 => x"FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15CFCDFF6F4",
INIT_32 => x"505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB047FFB0369",
INIT_33 => x"94F9A7F8A7F8A7F8A7F894F992FC55D5F94488F958F1F853EDFB52A8F84DBCFA",
INIT_34 => x"20205353455820524F4620342E312047554239305359530000000A0DFFFFFFFF",
INIT_35 => x"43502020043D5053202004202D20043F54414857043E040000000A0D4B04202D",
INIT_36 => x"20043D412020043D50442020043D58492020043D59492020043D53552020043D",
INIT_37 => x"0000000000000000000004315343565A4E4948464504203A43432020043D4220",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
 
port map (
do => data_out1,
dop(0) => dp1,
addr => addr(10 downto 0),
clk => clk,
di => data_in,
dip(0) => dp1,
en => cs1,
ssr => rst,
we => '0'
);
 
my_mon : process ( rw, addr, cs, data_out0, data_out1 )
begin
we <= not rw;
cs0 <= '0';
cs1 <= '0';
case addr(11) is
when '0' =>
cs0 <= cs;
data_out <= data_out0;
when '1' =>
cs1 <= cs;
data_out <= data_out1;
when others =>
null;
end case;
end process;
 
end architecture rtl;
 
/sys09xes_b4.vhd
0,0 → 1,362
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"8C02300D2780E12CF08E20C0022F60C10AF89FAD2086891F7F8406F89FAD02F0",
INIT_01 => x"CD8E040D0A3F2054414857BCF258EAF0463EF042946E29021635F08EF52635F0",
INIT_02 => x"B6B035EE261F30F6263F310A254700E0B6E2048E10E8038E30343B341F4AAF00",
INIT_03 => x"0235ED261F30F5263F310C25474700E0B6E2048E10E8038E02343034B03501E0",
INIT_04 => x"2E2E2E6B7369642045444920676E6974616D726F460D0AB03501E0B70235B035",
INIT_05 => x"6E20657669726420454449040D0A043F207265626D754E2065766972440D0A20",
INIT_06 => x"6574656C706D6F432074616D726F460D0A04202164657461636F6C6C6120746F",
INIT_07 => x"002510308169FF17FB2450FF1753F2BD89F08EBDF4BD04204B53494445444904",
INIT_08 => x"017FFB265A80A75F4F00028E3AF5BDFD008E0001F7891F3080E90022103381EF",
INIT_09 => x"F60101B601A70186846C042600814C0201B684A70101B600028E0201B7018601",
INIT_0a => x"028EC82600810101B601017C0201B70186D72600810201B602017C15F5BD0201",
INIT_0b => x"8EF1F4BDFFC64F00028E15F5BDFFC6FF86016F846F00028EF1F4BDFFC6FF8600",
INIT_0c => x"8E102034016F846F00028EF1F4BD03C64F00028E15F5BDFFC64F016F846F0002",
INIT_0d => x"FFC6FF861D88ED0101CC1B88ED0001F64F2035F72618C15C85A7A0A610C6E1F0",
INIT_0e => x"F5BD03C64F2588A707862488A707862388A701862188ED01FECC2688ED1F88ED",
INIT_0f => x"E0B7038639018500E0B653F27ECFF08E2503170201F70101B701C64F00F78E15"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"20DD8D0A2778850826018500E0B60A017F09017F0801B710863900E0B7118600",
INIT_01 => x"8500E0B6023439021A4FDC2608017AE12609017AE6260A017A39FD1C01E0B6E6",
INIT_02 => x"646F6D580A0D39F826048180A6E78D3901E0B70235F120B38DF5277885082602",
INIT_03 => x"706D6F432064616F6C70550A0D0464616F6C7055206B73694420454449206D65",
INIT_04 => x"626D754E2065766972440A0D04726F7272452064616F6C70550A0D046574656C",
INIT_05 => x"175AF28E04294E2F5928203F206572755320756F59206572410A0D043A207265",
INIT_06 => x"01B730802801221033812E01251030816AFF17FB293CFF178BFF1794F28E91FF",
INIT_07 => x"815F843DFF17FB290FFF175EFF17A5F28E4BFF17308B0001B66CFF1794F28E00",
INIT_08 => x"0101B701C64F00028E0401B701860601FF2DF4CEB10117B3265981FF0027104E",
INIT_09 => x"D501170201F60101B600028ED6002510E00017870117E0002510EA00170201F7",
INIT_0a => x"B00017570117B0002510BA00170201F70101B75C0201F60101B600028E710117",
INIT_0b => x"0101B75C0201F60101B600028E410117A501170201F60101B600028EA6002510",
INIT_0c => x"88E60B01B74C2688A600028E76002510800017270117800025108A00170201F7",
INIT_0d => x"01F70101B700028E5C0201F60101B60301176701170201F60101B60C01F75C27",
INIT_0e => x"00173701170201F60101B600028E38002510420017E90017420025104C001702",
INIT_0f => x"01F70101B701C64F00F78EC3260B01B14C01C6CB260C01F15C0201F60101B6D3"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"CE1BFE1715860A28EFFD170601FE403443FE1685F28E53F27E73F28E11011702",
INIT_01 => x"FAFD1706860826048139FA1C4DF4CE06260181C0350601FFED26C4ADF1202DF4",
INIT_02 => x"2DF4CEDDFD17158639FA1C63F4CE06260401B139FA1C39051A0326188139051A",
INIT_03 => x"350301B70301BB023439FA1C77F4CE0501B7808603017FEF260401B14339FA1C",
INIT_04 => x"043439041AFE1C2DF4CE04017C0B260301B139FA1C80A78EF4CE032605017A02",
INIT_05 => x"0600CC82357FFD170686023439FA1C2DF4CE8CFD1715860435011F80C45A101F",
INIT_06 => x"E4E606E1FD5A4F023401C64F668DD602160CE1FDE000CC1EE1FD0200CC1EE1FD",
INIT_07 => x"8E102034AC02170EE1FD2000CCE48D82355F04E1FD01C60AE1FD0001F608E1FD",
INIT_08 => x"8802170EE1FD3000CCC08D395F9502172035F4263F3180E700E1FCB202170001",
INIT_09 => x"0123038103A6395F7002172035F4263F3100E1FD80E68D02174F00018E102034",
INIT_0a => x"00000000000000000000000000000000000000000000395F03A6395F0001B74F",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"270281358D00C48E1000C3FDF18CECFFC0CE1000000000C00000000000000B20",
INIT_09 => x"5D891F158DD08CA71A8DD48CA71F8DEA20DA8CA7268DDE8CA72B8DF626168110",
INIT_0a => x"8D0B2784EC00C38E0F2600C48C10C920F5265A80A71435098D1434C58CAED927",
INIT_0b => x"C60AE1FD908CE608E1FDE4E606E1FD5A4F02349B9C6E39A0A604C38E109D2626",
INIT_0c => x"3F3180E700E1FC1E8D00018E102034178D0EE1FD2000CCE48D82355F04E1FD01",
INIT_0d => x"0039F92708C50EE1FC39F22740C50EE1FCF92680C50EE1FC395F028D2035F526",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(10 downto 0);
rdata : out std_logic_vector(7 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(3 downto 0);
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM00: RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E1074FE8E2EFA1AFB1EFB8FFBE0FCC5FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"0317A3FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031784FE8EB504",
INIT_03 => x"17408B981F6504175E86092C2081891FF1270D817F84370417B30217AAFE8E2E",
INIT_04 => x"20F00217ACFE8EF52674FE8C02300F2780E13BFE8E20C0022F60C15904175E04",
INIT_05 => x"17A4A6210417A50317211F650217B2FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317190417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131F703173F86FA031708",
INIT_08 => x"27A603170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265AA003172C031780A610C6A803172E0317E4AEEE0117B2FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A8903172E8602237E810425208180A610C6E1AE980317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E105803163F865B0317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"E1FD0200CC1EE1FD0600CC393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D0EE1FD20C60AE1FD08E1FD06E1FD5F04E1FD0100CC2E8D0CE1FDE000CC1E"
)
port map (
clk => clk,
en => en(0),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(0)
);
 
ROM01: RAMB4_S8
generic map (
INIT_00 => x"E1FCF92680C50EE1FC3B341F4AAF00C08EF42600C18C80E700E1FC218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F92708C50EE1FC39F22740C50E",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F7A02171186F9",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F2402161386E2DF732C02173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4EC0B02171286F9FCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017F3FE8E64E720C602",
INIT_08 => x"10347120028D396532C901171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016B301169035690017A4FE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB6FE8E39F726048180A651011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC8FE8EE12044AED78DCEFE8EB4001643A6E18DD4FE8EF42048AEEA8DC2FE8E",
INIT_0e => x"D02042A6B38DDFFE8ED92041A6BC8DDAFE8ECF204AAEC58DBCFE8ED82046AECE",
INIT_0f => x"B2FE8EBF8DB88DB08DA98DA18D27FF17B2FE8E900016EBFE8EC4A6AA8DE4FE8E"
)
port map (
clk => clk,
en => en(1),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(1)
);
 
ROM02: RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DCA00172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602346320078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"207F84048D0627E2DF7D00F09F6E8235F1265A518D558D2D860225E46880A608",
INIT_05 => x"DF9FA75186EE27018584A620E08E0926018584A6E0DFBEE0DF9FA7118610343F",
INIT_06 => x"2086008D8235018520E0B605260185E0DF9FA6E0DF9FA711860234903501A6E0",
INIT_07 => x"84A70386E0DFBE138D903501A70235F6260885FA27028584A6E0DFBE1234498D",
INIT_08 => x"02C6FDDFFD04E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A75186",
INIT_09 => x"20098D042420810D20608D0427FEDF7D30E08E16345986028D1B86FEDF7F01E7",
INIT_0a => x"890027100D81382716817C0027101A815A271B81342708819635AF001784A705",
INIT_0b => x"6D205A34275DFBDFFC8F0016792619C15CFBDFFC45260A810F270B8124270C81",
INIT_0c => x"598114273DC1FEDFF656200000CC5820212750814CFBDFB662204A2C27FBDFB6",
INIT_0d => x"2080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D81312754816E27",
INIT_0e => x"A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6ED224F81",
INIT_0f => x"C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF726508102"
)
port map (
clk => clk,
en => en(2),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(2)
);
 
ROM03: RAMB4_S8
generic map (
INIT_00 => x"2650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D5AEA2619",
INIT_01 => x"FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15CFCDFF6F4",
INIT_02 => x"505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB047FFB0369",
INIT_03 => x"94F9A7F8A7F8A7F8A7F894F992FC55D5F94488F958F1F853EDFB52A8F84DBCFA",
INIT_04 => x"20205353455820524F4620362E312047554239305359530000000A0DFFFFFFFF",
INIT_05 => x"43502020043D5053202004202D20043F54414857043E040000000A0D4B04202D",
INIT_06 => x"20043D412020043D50442020043D58492020043D59492020043D53552020043D",
INIT_07 => x"0000000000000000000004315343565A4E4948464504203A43432020043D4220",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
en => en(3),
we => we,
rst => rst,
addr => addr(8 downto 0),
di => wdata,
do => xdata(3)
);
 
rom_glue: process (cs, rw, addr, xdata)
begin
en <= (others=>'0');
case addr(10 downto 9) is
when "00" =>
en(0) <= cs;
rdata <= xdata(0);
when "01" =>
en(1) <= cs;
rdata <= xdata(1);
when "10" =>
en(2) <= cs;
rdata <= xdata(2);
when "11" =>
en(3) <= cs;
rdata <= xdata(3);
when others =>
null;
end case;
we <= not rw;
end process;
end architecture rtl;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.