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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path
    /System09/trunk/rtl/System09_Digilent_Atlys
    from Rev 161 to Rev 162
    Reverse comparison

Rev 161 → Rev 162

/system09.vhd
28,12 → 28,6
-- cpu09 (cpu09.vhd) CPU core
-- ACIA_6850 (acia6850.vhd) ACIA / UART
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
-- keyboard (keyboard.vhd) PS/2 Keyboard interface
-- (ps2_keyboard.vhd)
-- (keymap_rom_slice.vhd) Key map table
-- vdu8_mono (vdu8_mono.vhd) Monochrome VDU
-- (char_rom2k_b16.vhd)
-- (ram2k_b16.vhd)
-- timer (timer.vhd) Interrupt timer
-- trap (trap.vhd) Bus condition trap logic
-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system
49,9 → 43,6
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - IDE / Compact Flash interface
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Reserced for Parallel I/O (B5-X300)
133,26 → 124,21
library work;
use work.common.all;
library unisim;
use unisim.vcomponents.all;
use unisim.vcomponents.all;
 
entity system09 is
port(
CLKA : in Std_Logic; -- 100MHz Clock input
-- CLKB : in Std_Logic; -- 50MHz Clock input
SW2_N : in Std_logic; -- Master Reset input (active low)
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
 
 
 
-- RS232 Port
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
 
-- Status 7 segment LED
S : out std_logic_vector(7 downto 0)
 
 
-- CPU Debug Interface signals
-- cpu_reset_o : out Std_Logic;
-- cpu_clk_o : out Std_Logic;
194,8 → 180,6
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
constant VGA_CLK_DIV : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
226,11 → 210,6
signal RTS_n : Std_Logic;
signal CTS_n : Std_Logic;
 
-- keyboard port
signal keyboard_data_out : std_logic_vector(7 downto 0);
signal keyboard_cs : std_logic;
signal keyboard_irq : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_data_out : std_logic_vector(7 downto 0);
257,13 → 236,6
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red_o : std_logic;
signal vga_green_o : std_logic;
signal vga_blue_o : std_logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
288,15 → 260,8
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
 
-- Peripheral chip selects on Peripheral Bus
signal ide_cs : std_logic; -- IDE CF interface
signal ether_cs : std_logic; -- Ethernet interface
signal slot1_cs : std_logic; -- Expansion slot 1
signal slot2_cs : std_logic; -- Expansion slot 2
 
signal rst_i : std_logic; -- internal reset signal
signal clk_i : std_logic; -- internal master clock signal
signal lock : std_logic; -- SDRAM clock DLL lock indicator
 
-- signals that go through the SDRAM host-side interface
signal opBegun : std_logic; -- SDRAM operation started indicator
321,11 → 286,6
signal flash_ce_n : std_logic;
signal rs232_cts : Std_Logic;
signal rs232_rts : Std_Logic;
signal ether_cs_n : std_logic;
signal ether_aen : std_logic;
signal ether_bhe_n : std_logic;
signal slot1_cs_n : std_logic;
signal slot2_cs_n : std_logic;
-- signal BaudCount : std_logic_vector(5 downto 0);
 
333,8 → 293,6
signal clk_count : natural range 0 to CPU_CLK_DIV;
signal Clk25 : std_logic;
 
signal vga_clk : std_logic;
-----------------------------------------------------------------
--
-- CPU09 CPU core
439,9 → 397,6
);
end component;
 
 
 
 
----------------------------------------
--
-- Timer module
585,7 → 540,6
acia_clk => acia_clk
);
 
----------------------------------------
--
-- Timer Module
633,14 → 587,12
data_out => dat_addr(7 downto 0)
);
 
 
cpu_clk_buffer : BUFG
port map(
i => Clk25,
o => cpu_clk
);
 
----------------------------------------------------------------------
--
-- Process to decode memory map
652,8 → 604,6
rom_data_out,
flex_data_out,
acia_data_out,
keyboard_data_out,
vdu_data_out,
pb_data_out,
timer_data_out,
trap_data_out,
665,15 → 615,9
rom_cs <= '0';
flex_cs <= '0';
acia_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
pb_cs <= '0';
ide_cs <= '0';
ether_cs <= '0';
slot1_cs <= '0';
slot2_cs <= '0';
ram_cs <= '0';
 
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
711,20 → 655,6
--
 
--
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= keyboard_data_out;
keyboard_cs <= cpu_vma;
 
--
-- VDU port $E030 - $E03F
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
vdu_cs <= cpu_vma;
 
--
-- Reserved SWTPc MP-T Timer $E040 - $E04F
--
when "0100" => -- $E040
760,43 → 690,6
end case;
 
--
-- XST-3.0 Peripheral Bus goes here
-- $E100 to $E1FF
-- Four devices
-- IDE, Ethernet, Slot1, Slot2
--
when "0001" =>
cpu_data_in <= pb_data_out;
pb_cs <= cpu_vma;
case cpu_addr(7 downto 6) is
--
-- IDE Interface $E100 to $E13F
--
when "00" =>
ide_cs <= cpu_vma;
--
-- Ethernet Interface $E140 to $E17F
--
when "01" =>
ether_cs <= cpu_vma;
--
-- Slot 1 Interface $E180 to $E1BF
--
when "10" =>
slot1_cs <= cpu_vma;
--
-- Slot 2 Interface $E1C0 to $E1FF
--
when "11" =>
slot2_cs <= cpu_vma;
--
-- Nothing else
--
when others =>
null;
end case;
 
--
-- $E200 to $EFFF reserved for future use
--
when others =>
820,22 → 713,18
 
end process;
 
 
 
--
-- Interrupts and other bus control signals
--
interrupts : process( SW3_N,
pb_cs, pb_hold, pb_release, ram_hold,
-- ether_irq,
acia_irq,
keyboard_irq,
trap_irq,
timer_irq
)
begin
pb_hold <= pb_cs and (not pb_release);
cpu_irq <= acia_irq or keyboard_irq;
cpu_irq <= acia_irq;
cpu_nmi <= trap_irq or not( SW3_N );
cpu_firq <= timer_irq;
cpu_halt <= '0';
853,7 → 742,7
elsif rising_edge(clk_i) then
CountL <= CountL + 1;
end if;
-- S(7 downto 0) <= CountL(23 downto 16);
--S(7 downto 0) <= CountL(23 downto 16);
end process;
 
--
878,10 → 767,10
--
-- Reset button and reset timer
--
my_switch_assignments : process( rst_i, SW2_N, lock )
my_switch_assignments : process( rst_i, SW2_N)
begin
rst_i <= not SW2_N;
cpu_reset <= rst_i or (not lock);
cpu_reset <= rst_i;
end process;
 
--
897,26 → 786,6
end process;
 
--
-- Pin assignments for ethernet controller
--
my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
begin
ether_cs_n <= not ether_cs;
ether_aen <= not ether_cs; -- Ethernet address enable not
ether_bhe_n <= '1'; -- Ethernet bus high enable - 8 bit access only
end process;
 
--
-- I/O expansion slot assignments
--
my_slot_assignments : process( slot1_cs, slot2_cs)
begin
slot1_cs_n <= not slot1_cs;
slot2_cs_n <= not slot2_cs;
end process;
 
 
--
-- CPU read data request on rising CPU clock edge
--
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
944,13 → 813,17
end if;
end process;
 
status_leds : process( rst_i, cpu_reset, lock )
status_leds : process( rst_i, cpu_reset)
begin
S(0) <= rst_i;
S(1) <= cpu_reset;
S(2) <= lock;
S(3) <= countL(23);
S(7 downto 4) <= "0000";
S(7) <= rst_i;
S(6) <= cpu_reset;
S(2) <= countL(23);
S(3) <= countL(22);
S(4) <= countL(21);
S(5) <= countL(20);
S(1) <= '1'; -- countL(19);
S(0) <= '0'; -- countL(18);
--S(7 downto 4) <= "0000";
end process;
 
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,

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