OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /System09/trunk/rtl/System09_Digilent_Atlys
    from Rev 212 to Rev 209
    Reverse comparison

Rev 212 → Rev 209

/system09.prj
1,12 → 1,11
vhdl work "../Spartan6/keymap_rom512_b4.vhd"
vhdl work "../VHDL/ps2_keyboard.vhd"
vhdl work "../VHDL/bit_funcs.vhd"
verilog work "../Verilog/rgb2hdmi_encode.v"
vhdl work "../Spartan3/ram2k_b16.vhd"
vhdl work "../Spartan3/char_rom2k_b16.vhd"
vhdl work "../../src/sys09bug/sys09xes.vhd"
vhdl work "../../src/Flex9/flex9ram.vhd"
vhdl work "../VHDL/vdu8_hdmi.vhd"
vhdl work "../VHDL/vdu8.vhd"
vhdl work "../VHDL/trap.vhd"
vhdl work "../VHDL/timer.vhd"
vhdl work "../VHDL/keyboard.vhd"
/system09.ucf
42,10 → 42,7
# NET "UsbAdr<0>" LOC = "A14"; # Bank = 0, Pin name = IO_L62N_VREF, Sch name = U1-FIFOAD0
# NET "UsbAdr<1>" LOC = "B14"; # Bank = 0, Pin name = IO_L62P, Sch name = U1-FIFOAD1
# RS232 port
NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
 
# onBoard Quad-SPI Flash
# NET "FlashCLK" LOC = "R15"; # Bank = 2, Pin name = IO_L1P_CCLK_2, Sch name = SCK
# NET "FlashCS" LOC = "V3"; # Bank = 2, Pin name = IO_L65N_CSO_B_2, Sch name = CS
176,14 → 173,14
# NET "DDR2RZM" LOC="L6"; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT
 
# onboard HDMI OUT
NET "TMDSp_clock" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
NET "TMDSn_clock" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
NET "TMDSp[0]" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
NET "TMDSn[0]" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
NET "TMDSp[1]" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
NET "TMDSn[1]" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
NET "TMDSp[2]" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
NET "TMDSn[2]" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
# NET "TMDSp_clock" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
# NET "TMDSn_clock" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
# NET "TMDSp[0]" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
# NET "TMDSn[0]" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
# NET "TMDSp[1]" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
# NET "TMDSn[1]" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
# NET "TMDSp[2]" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
# NET "TMDSn[2]" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
# NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL
# NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA
 
238,7 → 235,16
# NET "JB<4>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = JA-CLK_N
# NET "JB<5>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = JA-CLK_P
# NET "JB<6>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, Sch name = JA-D1_N
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P
 
# PMOD Connector
# to J2 of Pmod-VGA (green-only VGA output)
NET "VGA_green[0]" LOC = "T3";
NET "VGA_green[1]" LOC = "R3";
NET "VGA_green[2]" LOC = "P6";
NET "VGA_green[3]" LOC = "N5";
NET "VGA_hsync_n" LOC = "V9";
NET "VGA_vsync_n" LOC = "T9";
 
# onboard VHDCI
# Channnel 1 connects to P signals, Channel 2 to N signals
284,4 → 290,9
# NET "VHDCIIO2<18>" LOC = "P7"; # Bank = 2, Pin name = *IO_L47N, Sch name = EXP-IO19_N
# NET "VHDCIIO2<19>" LOC = "V5"; # Bank = 2, Pin name = IO_49N_D4, Sch name = EXP-IO20_N
 
#
# SYSTEM09: RS232 PORT
#
NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
 
/system09.vhd
135,14 → 135,21
-- PS/2 Keyboard
ps2_clk : inout Std_logic;
ps2_dat : inout Std_Logic;
 
-- VGA port output
-- VGA_red : out std_logic_vector(3 downto 0);
VGA_green : out std_logic_vector(3 downto 0);
-- VGA_blue : out std_logic_vector(3 downto 0);
VGA_hsync_n : out std_logic;
VGA_vsync_n : out std_logic;
-- HDMI output
TMDSp_clock : out std_logic;
TMDSn_clock : out std_logic;
TMDSp : out std_logic_vector(2 downto 0);
TMDSn : out std_logic_vector(2 downto 0);
-- TMDSp_clock : out std_logic;
-- TMDSn_clock : out std_logic;
-- TMDSp : out std_logic_vector(2 downto 0);
-- TMDSn : out std_logic_vector(2 downto 0);
 
-- RS232 Port - via Atlys UART over USB (no h/w/ handshake available)
-- RS232 Port - via Pmod RS232
-- RS232_CTS : in Std_Logic;
-- RS232_RTS : out Std_Logic;
RS232_RXD : in Std_Logic;
244,7 → 251,12
-- Video Display Unit
signal vdu_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vdu_red : std_logic;
signal vdu_green : std_logic;
signal vdu_blue : std_logic;
signal vdu_hsync : std_logic;
signal vdu_vsync : std_logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
430,6 → 442,7
);
end component;
 
 
----------------------------------------
--
-- Video Display Unit.
436,7 → 449,7
--
----------------------------------------
 
component vdu8_hdmi
component vdu8
generic(
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
459,13 → 472,15
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
-- HDMI TMDS outputs
hdmi_clk : in std_logic;
TMDSp_clock : out std_logic;
TMDSn_clock : out std_logic;
TMDSp : out std_logic_vector(2 downto 0);
TMDSn : out std_logic_vector(2 downto 0)
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
710,7 → 725,7
o => vdu_clk
);
 
my_vdu : vdu8_hdmi
my_vdu : vdu8
generic map(
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
733,15 → 748,28
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
-- HDMI port connections
hdmi_clk => Clk25,
TMDSp => TMDSp,
TMDSn => TMDSn,
TMDSp_clock => TMDSp_clock,
TMDSn_clock => TMDSn_clock
vdu_data_out => vdu_data_out,
-- vga port connections
vga_clk => vdu_clk, -- 25 MHz VDU pixel clock
vga_red_o => vdu_red,
vga_green_o => vdu_green,
vga_blue_o => vdu_blue,
vga_hsync_o => vdu_hsync,
vga_vsync_o => vdu_vsync
);
 
--
-- VGA ouputs
--
my_vga_assignments : process( vdu_red, vdu_green, vdu_blue )
begin
VGA_green(0) <= vdu_green;
VGA_green(1) <= vdu_green;
VGA_green(2) <= vdu_green;
VGA_green(3) <= vdu_green;
end process;
VGA_hsync_n <= vdu_hsync;
VGA_vsync_n <= vdu_vsync;
 
----------------------------------------
--

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