URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/System09_Digilent_ZyboZ20
- from Rev 199 to Rev 200
- ↔ Reverse comparison
Rev 199 → Rev 200
/system09.gise
77,35 → 77,35
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970247" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611970197"> |
<transform xil_pn:end_ts="1612661069" xil_pn:in_ck="8828985201733018850" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1612661019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1611970247" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611970247"> |
<transform xil_pn:end_ts="1612661069" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1612661069"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611970256" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611970247"> |
<transform xil_pn:end_ts="1612661077" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1612661069"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
136,7 → 136,7
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611970295" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611970256"> |
<transform xil_pn:end_ts="1612661110" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1612661077"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
149,7 → 149,7
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611970334" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611970295"> |
<transform xil_pn:end_ts="1612661144" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1612661110"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
164,7 → 164,7
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611970369" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611970334"> |
<transform xil_pn:end_ts="1612661178" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1612661144"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
177,7 → 177,7
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611970334" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611970320"> |
<transform xil_pn:end_ts="1612661144" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1612661132"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
/system09.ipf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
system09.ipf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: system09.prj
===================================================================
--- system09.prj (revision 199)
+++ system09.prj (revision 200)
@@ -1,6 +1,9 @@
vhdl work "../VHDL/bit_funcs.vhd"
+vhdl work "../Spartan3/ram2k_b16.vhd"
+vhdl work "../Spartan3/char_rom2k_b16.vhd"
vhdl work "../../src/sys09bug/sys09swt.vhd"
vhdl work "../../src/Flex9/flex9ram.vhd"
+vhdl work "../VHDL/vdu8.vhd"
vhdl work "../VHDL/trap.vhd"
vhdl work "../VHDL/timer.vhd"
vhdl work "../VHDL/datram.vhd"
Index: system09.ucf
===================================================================
--- system09.ucf (revision 199)
+++ system09.ucf (revision 200)
@@ -136,8 +136,25 @@
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_data_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
+
+# NET "TMDS_Clk_p" LOC = "H16"; # Clock p
+# NET "TMDS_Clk_n" LOC = "H17"; # Clock n
+# NET "TMDS_Data_p[2]" LOC = "B19"; #
+# NET "TMDS_Data_n[2]" LOC = "A20"; # Red
+# NET "TMDS_Data_p[1]" LOC = "C20"; #
+# NET "TMDS_Data_n[1]" LOC = "B20"; # Green
+# NET "TMDS_Data_p[0]" LOC = "D19"; #
+# NET "TMDS_Data_n[0]" LOC = "D20"; # Blue
+
+# NET "TMDS_Clk_p" IOSTANDARD = TMDS_33;
+# NET "TMDS_Clk_n" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_p[2]" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_n[2]" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_p[1]" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_n[1]" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_p[0]" IOSTANDARD = TMDS_33;
+# NET "TMDS_Data_n[0]" IOSTANDARD = TMDS_33;
-
#HDMI TX CEC
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
@@ -183,8 +200,21 @@
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
+
+# Temp VGA output (the raw output from VDU8)
+NET "red" LOC = "T14";
+NET "red" IOSTANDARD = LVCMOS33;
+NET "green" LOC = "T15";
+NET "green" IOSTANDARD = LVCMOS33;
+NET "blue" LOC = "P14";
+NET "blue" IOSTANDARD = LVCMOS33;
+NET "hsync" LOC = "R14";
+NET "hsync" IOSTANDARD = LVCMOS33;
+NET "vsync" LOC = "U14";
+NET "vsync" IOSTANDARD = LVCMOS33;
+NET "blank" LOC = "U15";
+NET "blank" IOSTANDARD = LVCMOS33;
-
##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
/system09.vhd
82,7 → 82,15
RS232_RTS : out Std_Logic; |
RS232_RXD : in Std_Logic; |
RS232_TXD : out Std_Logic; |
|
|
-- TMDS_Clk_p : out std_logic; |
-- TMDS_Clk_n : out std_logic; |
-- TMDS_Data_p : out std_logic_vector(2 downto 0); |
-- TMDS_Data_n : out std_logic_vector(2 downto 0); |
|
-- raw output from VDU8 |
red, green, blue, hsync, vsync, blank : out std_logic; |
|
-- slide switches |
sw : in std_logic_vector(3 downto 0); |
-- push buttons [Unused, Single-Step, NMI, RESET] |
104,7 → 112,9
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz) |
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock |
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant BAUD_RATE : integer := 57600; -- Baud Rate |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; |
|
159,7 → 169,22
-- Dynamic Address Translation |
signal dat_cs : std_logic; |
signal dat_addr : std_logic_vector(7 downto 0); |
|
|
-- Video Display Unit (single-bit for each RGB color) |
signal vdu_cs : std_logic; |
signal vdu_data_out : std_logic_vector(7 downto 0); |
signal vga_red_o : std_logic; |
signal vga_green_o : std_logic; |
signal vga_blue_o : std_logic; |
signal vga_blank_o : std_logic; -- new signal |
-- original VGA interface |
signal vga_vsync_n : Std_Logic; |
signal vga_hsync_n : Std_Logic; |
signal VGA_blue : std_logic_vector(7 downto 0); |
signal VGA_green : std_logic_vector(7 downto 0); |
signal VGA_red : std_logic_vector(7 downto 0); |
signal vid_pData : std_logic_vector(23 downto 0); |
signal serial_clk_unused : std_logic; |
-- timer |
signal timer_data_out : std_logic_vector(7 downto 0); |
signal timer_cs : std_logic; |
175,9 → 200,9
|
signal CountL : std_logic_vector(25 downto 0); |
signal clk_count : natural range 0 to CPU_CLK_DIV; |
signal Clk25 : std_logic; |
signal Clk25 : std_logic; |
signal vga_clk : std_logic; |
|
|
component btn_debounce |
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0); |
CLK : in STD_LOGIC; |
327,7 → 352,51
ACIA_clk : out Std_logic -- ACIA Clock output |
); |
end component; |
|
|
---------------------------------------- |
-- |
-- Video Display Unit. |
-- |
---------------------------------------- |
|
component vdu8 |
generic( |
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ |
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ |
VGA_HOR_CHARS : integer := 80; -- CHARACTERS |
VGA_VER_CHARS : integer := 25; -- CHARACTERS |
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS |
VGA_LIN_PER_CHAR : integer := 16; -- LINES |
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS |
VGA_HOR_SYNC : integer := 96; -- PIXELS |
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS |
VGA_VER_BACK_PORCH : integer := 13; -- LINES |
VGA_VER_SYNC : integer := 2; -- LINES |
VGA_VER_FRONT_PORCH : integer := 35 -- LINES |
); |
port( |
-- control register interface |
vdu_clk : in std_logic; -- CPU Clock - 25MHz |
vdu_rst : in std_logic; |
vdu_cs : in std_logic; |
vdu_rw : in std_logic; |
vdu_addr : in std_logic_vector(2 downto 0); |
vdu_data_in : in std_logic_vector(7 downto 0); |
vdu_data_out : out std_logic_vector(7 downto 0); |
|
-- vga port connections |
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz |
vga_red_o : out std_logic; |
vga_green_o : out std_logic; |
vga_blue_o : out std_logic; |
vga_blank_o : out std_logic; -- new signal "blank" |
vga_hsync_o : out std_logic; |
vga_vsync_o : out std_logic |
); |
end component; |
|
|
---------------------------------------- |
-- |
-- Timer module |
544,6 → 613,45
clk => clk_i, |
acia_clk => acia_clk |
); |
|
---------------------------------------- |
-- |
-- Video Display Unit instantiation |
-- |
---------------------------------------- |
my_vdu : vdu8 |
generic map( |
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ |
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ |
VGA_HOR_CHARS => 80, -- CHARACTERS |
VGA_VER_CHARS => 25, -- CHARACTERS |
VGA_PIX_PER_CHAR => 8, -- PIXELS |
VGA_LIN_PER_CHAR => 16, -- LINES |
VGA_HOR_BACK_PORCH => 40, -- PIXELS |
VGA_HOR_SYNC => 96, -- PIXELS |
VGA_HOR_FRONT_PORCH => 24, -- PIXELS |
VGA_VER_BACK_PORCH => 13, -- LINES |
VGA_VER_SYNC => 2, -- LINES |
VGA_VER_FRONT_PORCH => 35 -- LINES |
) |
port map( |
-- Control Registers |
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in |
vdu_rst => cpu_reset, |
vdu_cs => vdu_cs, |
vdu_rw => cpu_rw, |
vdu_addr => cpu_addr(2 downto 0), |
vdu_data_in => cpu_data_out, |
vdu_data_out => vdu_data_out, |
-- vga port connections |
vga_clk => vga_clk, -- 25 MHz VDU pixel clock |
vga_red_o => red, |
vga_green_o => green, |
vga_blue_o => blue, |
vga_blank_o => blank, -- new signal |
vga_hsync_o => hsync, |
vga_vsync_o => vsync |
); |
|
---------------------------------------- |
-- |
609,6 → 717,7
rom_data_out, |
flex_data_out, |
acia_data_out, |
vdu_data_out, |
timer_data_out, |
trap_data_out, |
ram1_data_out, ram2_data_out |
618,7 → 727,8
dat_cs <= '0'; |
rom_cs <= '0'; |
flex_cs <= '0'; |
acia_cs <= '0'; |
acia_cs <= '0'; |
vdu_cs <= '0'; |
timer_cs <= '0'; |
trap_cs <= '0'; |
ram1_cs <= '0'; |
657,8 → 767,14
-- Reserved |
-- Floppy Disk Controller port $E010 - $E01F |
-- |
|
-- |
-- VDU port $E030 - $E03F |
-- |
when "0011" => -- $E030 |
cpu_data_in <= vdu_data_out; |
vdu_cs <= cpu_vma; |
|
-- |
-- Reserved SWTPc MP-T Timer $E040 - $E04F |
-- |
when "0100" => -- $E040 |
/system09.xise
17,39 → 17,39
<files> |
<file xil_pn:name="common.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
</file> |
<file xil_pn:name="../VHDL/timer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="../../src/Flex9/flex9ram.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="../VHDL/ACIA_Clock.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="../VHDL/acia6850.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
</file> |
<file xil_pn:name="../../src/sys09bug/sys09swt.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="../VHDL/datram.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="../VHDL/trap.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="../VHDL/cpu09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
</file> |
<file xil_pn:name="../VHDL/bit_funcs.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> |
57,15 → 57,15
</file> |
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> |
</file> |
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> |
</file> |
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> |
</file> |
<file xil_pn:name="system09.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
72,8 → 72,20
</file> |
<file xil_pn:name="btn_debounce.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
</file> |
<file xil_pn:name="../Spartan3/ram2k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../Spartan3/char_rom2k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../VHDL/vdu8.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
</files> |
|
<properties> |