OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path 
    /System09/trunk/rtl/System09_Digilent_ZyboZ20
    from Rev 200 to Rev 202
    ↔ Reverse comparison
  •

Rev 200 → Rev 202

/system09.gise
77,35 → 77,35
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661019" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841491" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661069" xil_pn:in_ck="8828985201733018850" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1612661019">
<transform xil_pn:end_ts="1613841544" xil_pn:in_ck="6056042413176164820" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1613841491">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1612661069" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1612661069">
<transform xil_pn:end_ts="1613841544" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1613841544">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1612661077" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1612661069">
<transform xil_pn:end_ts="1613841553" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1613841544">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
136,7 → 136,7
<outfile xil_pn:name="system09.ngd"/>
<outfile xil_pn:name="system09_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1612661110" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1612661077">
<transform xil_pn:end_ts="1613841591" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1613841553">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
149,7 → 149,7
<outfile xil_pn:name="system09_summary.xml"/>
<outfile xil_pn:name="system09_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1612661144" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1612661110">
<transform xil_pn:end_ts="1613841628" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1613841591">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
164,7 → 164,7
<outfile xil_pn:name="system09_pad.txt"/>
<outfile xil_pn:name="system09_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1612661178" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1612661144">
<transform xil_pn:end_ts="1613841663" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1613841628">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
177,7 → 177,7
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1612661144" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1612661132">
<transform xil_pn:end_ts="1613841628" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1613841615">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/system09.ipf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/system09.prj
1,7 → 1,7
vhdl work "../VHDL/bit_funcs.vhd"
vhdl work "../Spartan3/ram2k_b16.vhd"
vhdl work "../Spartan3/char_rom2k_b16.vhd"
vhdl work "../../src/sys09bug/sys09swt.vhd"
vhdl work "../../src/sys09bug/sys09xes.vhd"
vhdl work "../../src/Flex9/flex9ram.vhd"
vhdl work "../VHDL/vdu8.vhd"
vhdl work "../VHDL/trap.vhd"
/system09.ucf
21,13 → 21,13
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
NET "sw[0]" LOC = "G15";
NET "sw[0]" IOSTANDARD = LVCMOS33;
NET "sw[0]" IOSTANDARD = LVCMOS33;
NET "sw[1]" LOC = "P15";
NET "sw[1]" IOSTANDARD = LVCMOS33;
NET "sw[1]" IOSTANDARD = LVCMOS33;
NET "sw[2]" LOC = "W13";
NET "sw[2]" IOSTANDARD = LVCMOS33;
NET "sw[2]" IOSTANDARD = LVCMOS33;
NET "sw[3]" LOC = "T16";
NET "sw[3]" IOSTANDARD = LVCMOS33;
NET "sw[3]" IOSTANDARD = LVCMOS33;
 
##Buttons
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
35,13 → 35,13
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
NET "btn[0]" LOC = "K18";
NET "btn[0]" IOSTANDARD = LVCMOS33;
NET "btn[0]" IOSTANDARD = LVCMOS33;
NET "btn[1]" LOC = "P16";
NET "btn[1]" IOSTANDARD = LVCMOS33;
NET "btn[1]" IOSTANDARD = LVCMOS33;
NET "btn[2]" LOC = "K19";
NET "btn[2]" IOSTANDARD = LVCMOS33;
NET "btn[2]" IOSTANDARD = LVCMOS33;
NET "btn[3]" LOC = "Y16";
NET "btn[3]" IOSTANDARD = LVCMOS33;
NET "btn[3]" IOSTANDARD = LVCMOS33;
 
##LEDs
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
49,21 → 49,21
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
NET "led[0]" LOC = "M14";
NET "led[0]" IOSTANDARD = LVCMOS33;
NET "led[0]" DRIVE = 12;
NET "led[0]" SLEW = SLOW;
NET "led[0]" IOSTANDARD = LVCMOS33;
NET "led[0]" DRIVE = 12;
NET "led[0]" SLEW = SLOW;
NET "led[1]" LOC = "M15";
NET "led[1]" IOSTANDARD = LVCMOS33;
NET "led[1]" DRIVE = 12;
NET "led[1]" SLEW = SLOW;
NET "led[1]" IOSTANDARD = LVCMOS33;
NET "led[1]" DRIVE = 12;
NET "led[1]" SLEW = SLOW;
NET "led[2]" LOC = "G14";
NET "led[2]" IOSTANDARD = LVCMOS33;
NET "led[2]" DRIVE = 12;
NET "led[2]" SLEW = SLOW;
NET "led[2]" IOSTANDARD = LVCMOS33;
NET "led[2]" DRIVE = 12;
NET "led[2]" SLEW = SLOW;
NET "led[3]" LOC = "D18";
NET "led[3]" IOSTANDARD = LVCMOS33;
NET "led[3]" DRIVE = 12;
NET "led[3]" SLEW = SLOW;
NET "led[3]" IOSTANDARD = LVCMOS33;
NET "led[3]" DRIVE = 12;
NET "led[3]" SLEW = SLOW;
 
 
##RGB LED 5 (Zybo Z7-20 only)
179,7 → 179,6
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
188,9 → 187,25
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
# PmodVGA Connector J1 to Zybo JC
NET "VGA_red[0]" LOC = "V15";
NET "VGA_red[0]" IOSTANDARD = LVCMOS33;
NET "VGA_red[1]" LOC = "W15";
NET "VGA_red[1]" IOSTANDARD = LVCMOS33;
NET "VGA_red[2]" LOC = "T11";
NET "VGA_red[2]" IOSTANDARD = LVCMOS33;
NET "VGA_red[3]" LOC = "T10";
NET "VGA_red[3]" IOSTANDARD = LVCMOS33;
NET "VGA_blue[0]" LOC = "W14";
NET "VGA_blue[0]" IOSTANDARD = LVCMOS33;
NET "VGA_blue[1]" LOC = "Y14";
NET "VGA_blue[1]" IOSTANDARD = LVCMOS33;
NET "VGA_blue[2]" LOC = "T12";
NET "VGA_blue[2]" IOSTANDARD = LVCMOS33;
NET "VGA_blue[3]" LOC = "U12";
NET "VGA_blue[3]" IOSTANDARD = LVCMOS33;
 
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
199,22 → 214,21
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
 
# Temp VGA output (the raw output from VDU8)
NET "red" LOC = "T14";
NET "red" IOSTANDARD = LVCMOS33;
NET "green" LOC = "T15";
NET "green" IOSTANDARD = LVCMOS33;
NET "blue" LOC = "P14";
NET "blue" IOSTANDARD = LVCMOS33;
NET "hsync" LOC = "R14";
NET "hsync" IOSTANDARD = LVCMOS33;
NET "vsync" LOC = "U14";
NET "vsync" IOSTANDARD = LVCMOS33;
NET "blank" LOC = "U15";
NET "blank" IOSTANDARD = LVCMOS33;
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
# PmodVGA Connector J2 to Zybo JD
NET "VGA_green[0]" LOC = "T14";
NET "VGA_green[0]" IOSTANDARD = LVCMOS33;
NET "VGA_green[1]" LOC = "T15";
NET "VGA_green[1]" IOSTANDARD = LVCMOS33;
NET "VGA_green[2]" LOC = "P14";
NET "VGA_green[2]" IOSTANDARD = LVCMOS33;
NET "VGA_green[3]" LOC = "R14";
NET "VGA_green[3]" IOSTANDARD = LVCMOS33;
NET "VGA_hsync_n" LOC = "U14";
NET "VGA_hsync_n" IOSTANDARD = LVCMOS33;
NET "VGA_vsync_n" LOC = "U15";
NET "VGA_vsync_n" IOSTANDARD = LVCMOS33;
##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
223,10 → 237,8
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
##Pmod Header JE
 
##PmodRS232
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
##PmodRS232 to Zybo JE
# Pin Dir Function PMOD Dir Function PinLoc
# 1 input CTS je<0> output CTS W16
# 2 output RTS je<1> input RTS V12
235,19 → 247,18
# 5 GND
# 6 VCC
# NET "RS232_RTS" LOC = "V12";
# NET "RS232_RTS" IOSTANDARD = LVCMOS33;
# NET "RS232_RTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" LOC = "W16";
# NET "RS232_CTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" DRIVE = 12;
# NET "RS232_CTS" SLEW = SLOW;
# NET "RS232_CTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" DRIVE = 12;
# NET "RS232_CTS" SLEW = SLOW;
# NET "RS232_RXD" LOC = "J15";
# NET "RS232_RXD" IOSTANDARD = LVCMOS33;
# NET "RS232_RXD" IOSTANDARD = LVCMOS33;
# NET "RS232_TXD" LOC = "H15";
# NET "RS232_TXD" IOSTANDARD = LVCMOS33;
# NET "RS232_TXD" DRIVE = 12;
# NET "RS232_TXD" SLEW = SLOW;
 
# PmodUSBUART Zybo Pmod Port JE
# NET "RS232_TXD" IOSTANDARD = LVCMOS33;
# NET "RS232_TXD" DRIVE = 12;
# NET "RS232_TXD" SLEW = SLOW;
# PmodUSBUART to Zybo JE
# Pin Dir Function PMOD Dir Function PinLoc
# 1 output RTS je<0> input CTS V12
# 2 input RXD je<1> output TXD W16
256,17 → 267,17
# 5 GND
# 6 SYS3V3 (make sure Pmod jumper JP1 is LCL-VCC not VCC-SYS to avoid driving 3.3V onto Zybo board)
NET "RS232_RTS" LOC = "H15";
NET "RS232_RTS" IOSTANDARD = LVCMOS33;
NET "RS232_RTS" DRIVE = 12;
NET "RS232_RTS" SLEW = SLOW;
NET "RS232_RTS" IOSTANDARD = LVCMOS33;
NET "RS232_RTS" DRIVE = 12;
NET "RS232_RTS" SLEW = SLOW;
NET "RS232_CTS" LOC = "V12";
NET "RS232_CTS" IOSTANDARD = LVCMOS33;
NET "RS232_CTS" IOSTANDARD = LVCMOS33;
NET "RS232_RXD" LOC = "J15";
NET "RS232_RXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "W16";
NET "RS232_TXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" DRIVE = 12;
NET "RS232_TXD" SLEW = SLOW;
NET "RS232_RXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "W16";
NET "RS232_TXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" DRIVE = 12;
NET "RS232_TXD" SLEW = SLOW;
 
##Pcam MIPI CSI-2 Connector
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
/system09.vhd
88,8 → 88,12
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
-- TMDS_Data_n : out std_logic_vector(2 downto 0);
 
-- raw output from VDU8
red, green, blue, hsync, vsync, blank : out std_logic;
-- CRTC output signals
VGA_vsync_n : out Std_Logic;
VGA_hsync_n : out Std_Logic;
VGA_blue : out std_logic_vector(3 downto 0);
VGA_green : out std_logic_vector(3 downto 0);
VGA_red : out std_logic_vector(3 downto 0);
-- slide switches
sw : in std_logic_vector(3 downto 0);
114,7 → 118,7
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/VGA_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
170,20 → 174,13
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit (single-bit for each RGB color)
-- Video Display Unit
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red_o : std_logic;
signal vga_green_o : std_logic;
signal vga_blue_o : std_logic;
signal vga_blank_o : std_logic; -- new signal
-- original VGA interface
signal vga_vsync_n : Std_Logic;
signal vga_hsync_n : Std_Logic;
signal VGA_blue : std_logic_vector(7 downto 0);
signal VGA_green : std_logic_vector(7 downto 0);
signal VGA_red : std_logic_vector(7 downto 0);
signal vid_pData : std_logic_vector(23 downto 0);
 
signal serial_clk_unused : std_logic;
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
389,8 → 386,7
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_blank_o : out std_logic; -- new signal "blank"
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
645,13 → 641,31
vdu_data_out => vdu_data_out,
-- vga port connections
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
vga_red_o => red,
vga_green_o => green,
vga_blue_o => blue,
vga_blank_o => blank, -- new signal
vga_hsync_o => hsync,
vga_vsync_o => vsync
vga_red_o => vga_red_o,
vga_green_o => vga_green_o,
vga_blue_o => vga_blue_o,
vga_hsync_o => VGA_hsync_n,
vga_vsync_o => VGA_vsync_n
);
--
-- VGA ouputs
--
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
begin
VGA_red(0) <= vga_red_o;
VGA_red(1) <= vga_red_o;
VGA_red(2) <= vga_red_o;
VGA_red(3) <= vga_red_o;
VGA_green(0) <= vga_green_o;
VGA_green(1) <= vga_green_o;
VGA_green(2) <= vga_green_o;
VGA_green(3) <= vga_green_o;
VGA_blue(0) <= vga_blue_o;
VGA_blue(1) <= vga_blue_o;
VGA_blue(2) <= vga_blue_o;
VGA_blue(3) <= vga_blue_o;
end process;
 
 
----------------------------------------
--
705,7 → 719,11
i => Clk25,
o => cpu_clk
);
vga_clk_buffer : BUFG
port map(
i => Clk25,
o => vga_clk
);
----------------------------------------------------------------------
--
-- Process to decode memory map
/system09.xise
35,10 → 35,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../src/sys09bug/sys09swt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../VHDL/datram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
86,6 → 82,10
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../src/sys09bug/sys09xes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
</files>
 
<properties>

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