URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/System09_Digilent_ZyboZ20
- from Rev 207 to Rev 208
- ↔ Reverse comparison
Rev 207 → Rev 208
/system09.gise
77,35 → 77,35
</files> |
|
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1613845693" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1613845693"> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
136,9 → 136,11
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1613845739" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1613845703"> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="system09.pcf"/> |
<outfile xil_pn:name="system09_map.map"/> |
149,7 → 151,7
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1613845775" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1613845739"> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
164,10 → 166,12
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="system09.bgn"/> |
<outfile xil_pn:name="system09.bit"/> |
177,7 → 181,7
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
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<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
/system09.ipf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/system09.prj
12,6 → 12,4
vhdl work "../VHDL/acia6850.vhd" |
vhdl work "common.vhd" |
vhdl work "btn_debounce.vhd" |
vhdl work "../Spartan3/ram32k_b16.vhd" |
vhdl work "../Spartan3/ram16k_b16.vhd" |
vhdl work "system09.vhd" |
/system09.vhd
270,6 → 270,27
|
---------------------------------------- |
-- |
-- Parameterized Block RAM |
-- |
---------------------------------------- |
|
component block_spram |
generic ( |
dwidth : integer := 8; -- parameterized data width |
awidth : integer := 16 -- parameterized address width |
); |
port ( |
clk : in std_logic; |
cs : in std_logic; -- chip-select/enable |
addr : in std_logic_vector(awidth-1 downto 0); |
rw : in std_logic; |
data_in : in std_logic_vector(dwidth-1 downto 0); |
data_out : out std_logic_vector(dwidth-1 downto 0) |
); |
end component; |
|
---------------------------------------- |
-- |
-- 32KBytes Block RAM 0000 |
-- $0000 - $7FFF |
-- |
546,10 → 567,11
data_in => cpu_data_out |
); |
|
my_32k : ram_32k |
my_32k : block_spram |
generic map (dwidth => 8, awidth => 15) |
port map ( |
clk => cpu_clk, |
rst => cpu_reset, |
--rst => cpu_reset, |
cs => ram1_cs, |
rw => cpu_rw, |
addr => cpu_addr(14 downto 0), |
557,10 → 579,11
data_in => cpu_data_out |
); |
|
my_16k : ram_16k |
my_16k : block_spram |
generic map (dwidth => 8, awidth => 14) |
port map ( |
clk => cpu_clk, |
rst => cpu_reset, |
--rst => cpu_reset, |
cs => ram2_cs, |
rw => cpu_rw, |
addr => cpu_addr(13 downto 0), |
/system09.xise
53,16 → 53,8
</file> |
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> |
</file> |
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> |
</file> |
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> |
</file> |
<file xil_pn:name="system09.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
78,8 → 70,11
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="../Spartan6/block_spram.vhd" xil_pn:type="FILE_VHDL"/> |
<file xil_pn:name="../XilinxRAMs/block_spram.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="../XilinxRAMs/block_spram.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |