OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /System09/trunk/rtl/System09_base
    from Rev 132 to Rev 137
    Reverse comparison

Rev 132 → Rev 137

/Makefile
139,7 → 139,7
clean:
-$(MAKE) -C ../../src/sys09bug clean
-$(MAKE) -C ../../src/Flex9 clean
-$(RM) *.ncd *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp *.ptwx *_map.map
-$(RM) *.ncd *.cfi *_bitgen.xwbt *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp *.ptwx *_map.map
-$(RM) *.ncl *.ngm *.prm *_pad.txt *.twx *.log *.syr *.par *.exo *.xpi *.xrpt *.xml
-$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn tmp.ut
-$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc
/system09.vhd
88,12 → 88,12
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 2.0 - 2 September 2004 - John Kent
-- ported to Digilent Xilinx Spartan3 starter board
-- removed Compact Flash and Trap Logic.
-- removed Compact Flash and Trap Logic.
-- Replaced SBUG with KBug9s
--
-- Version 3.0 - 29th August 2006 - John Kent
131,8 → 131,8
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library work;
use work.common.all;
use WORK.xsasdram.all;
use work.common.all;
use WORK.xsasdram.all;
library unisim;
use unisim.vcomponents.all;
 
140,15 → 140,15
port(
CLKA : in Std_Logic; -- 100MHz Clock input
-- CLKB : in Std_Logic; -- 50MHz Clock input
SW2_N : in Std_logic; -- Master Reset input (active low)
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
SW2_N : in Std_logic; -- Master Reset input (active low)
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
 
-- PS/2 Keyboard
ps2_clk : inout Std_logic;
ps2_dat : inout Std_Logic;
-- PS/2 Keyboard
ps2_clk : inout Std_logic;
ps2_dat : inout Std_Logic;
 
-- CRTC output signals
vga_vsync_n : out Std_Logic;
-- CRTC output signals
vga_vsync_n : out Std_Logic;
vga_hsync_n : out Std_Logic;
vga_blue : out std_logic_vector(2 downto 0);
vga_green : out std_logic_vector(2 downto 0);
155,13 → 155,13
vga_red : out std_logic_vector(2 downto 0);
 
-- RS232 Port
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
RS232_CTS : in Std_Logic;
RS232_RTS : out Std_Logic;
 
-- Status 7 segment LED
S : out std_logic_vector(7 downto 0);
-- Status 7 segment LED
S : out std_logic_vector(7 downto 0);
 
-- SDRAM side
SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays
177,7 → 177,7
SDRAM_DQMH : out std_logic; -- enable upper-byte of SDRAM databus if true
SDRAM_DQML : out std_logic; -- enable lower-byte of SDRAM databus if true
 
-- Peripheral I/O bus $E100 - $E1FF
-- Peripheral I/O bus $E100 - $E1FF
PB_RD_N : out std_logic;
PB_WR_N : out std_logic;
PB_A : out std_logic_vector(4 downto 0);
185,8 → 185,8
 
-- IDE Compact Flash $E100 - $E13F
ide_dmack_n : out std_logic;
ide_cs0_n : out std_logic;
ide_cs1_n : out std_logic;
ide_cs0_n : out std_logic;
ide_cs1_n : out std_logic;
 
-- Ethernet $E140 - $E17F
ether_cs_n : out std_logic;
197,12 → 197,12
ether_irq : in std_logic; -- Ethernet irq - Shared with BAR6
 
-- Slot 1 $E180 - $E1BF
slot1_cs_n : out std_logic;
-- slot1_irq : in std_logic;
slot1_cs_n : out std_logic;
-- slot1_irq : in std_logic;
 
-- Slot 2 $E1C0 - $E1FF
slot2_cs_n : out std_logic;
-- slot2_irq : in std_logic;
slot2_cs_n : out std_logic;
-- slot2_irq : in std_logic;
 
-- CPU Debug Interface signals
-- cpu_reset_o : out Std_Logic;
218,9 → 218,9
-- cpu_data_in_o : out std_logic_vector(7 downto 0);
-- cpu_data_out_o : out std_logic_vector(7 downto 0);
-- Disable Flash
FLASH_CE_N : out std_logic
);
-- Disable Flash
FLASH_CE_N : out std_logic
);
end system09;
 
-------------------------------------------------------------------------------
249,7 → 249,7
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
constant VGA_CLK_DIV : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
constant TRESET : natural := 300; -- min initialization interval (us)
287,7 → 287,7
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_data_out : std_logic_vector(7 downto 0);
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
signal ram_hold : std_logic; -- hold off slow accesses
signal ram_release : std_logic; -- Release ram hold
329,13 → 329,13
 
-- Peripheral Bus port
signal pb_data_out : std_logic_vector(7 downto 0);
signal pb_cs : std_logic; -- peripheral bus chip select
signal pb_wru : std_logic; -- upper byte write strobe
signal pb_wrl : std_logic; -- lower byte write strobe
signal pb_rdu : std_logic; -- upper byte read strobe
signal pb_rdl : std_logic; -- lower byte read strobe
signal pb_hold : std_logic; -- hold peripheral bus access
signal pb_release : std_logic; -- release hold of peripheral bus
signal pb_cs : std_logic; -- peripheral bus chip select
signal pb_wru : std_logic; -- upper byte write strobe
signal pb_wrl : std_logic; -- lower byte write strobe
signal pb_rdu : std_logic; -- upper byte read strobe
signal pb_rdl : std_logic; -- lower byte read strobe
signal pb_hold : std_logic; -- hold peripheral bus access
signal pb_release : std_logic; -- release hold of peripheral bus
signal pb_count : std_logic_vector(3 downto 0); -- hold counter
signal pb_hold_state : hold_state_type;
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
343,9 → 343,9
 
-- Peripheral chip selects on Peripheral Bus
signal ide_cs : std_logic; -- IDE CF interface
signal ether_cs : std_logic; -- Ethernet interface
signal slot1_cs : std_logic; -- Expansion slot 1
signal slot2_cs : std_logic; -- Expansion slot 2
signal ether_cs : std_logic; -- Ethernet interface
signal slot1_cs : std_logic; -- Expansion slot 1
signal slot2_cs : std_logic; -- Expansion slot 2
 
signal rst_i : std_logic; -- internal reset signal
signal clk_i : std_logic; -- internal master clock signal
368,7 → 368,7
type ram_type is (ram_state_0,
ram_state_rd1, ram_state_rd2,
ram_state_wr1,
ram_state_3 );
ram_state_3 );
signal ram_state : ram_type;
 
 
386,18 → 386,18
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
vma: out std_logic;
addr: out std_logic_vector(15 downto 0);
rw: out std_logic; -- Asynchronous memory interface
data_out: out std_logic_vector(7 downto 0);
data_in: in std_logic_vector(7 downto 0);
irq: in std_logic;
firq: in std_logic;
nmi: in std_logic;
halt: in std_logic;
hold: in std_logic
clk: in std_logic;
rst: in std_logic;
vma: out std_logic;
addr: out std_logic_vector(15 downto 0);
rw: out std_logic; -- Asynchronous memory interface
data_out: out std_logic_vector(7 downto 0);
data_in: in std_logic_vector(7 downto 0);
irq: in std_logic;
firq: in std_logic;
nmi: in std_logic;
halt: in std_logic;
hold: in std_logic
);
end component;
 
410,9 → 410,9
component mon_rom
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (11 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_in : in std_logic_vector (7 downto 0)
473,11 → 473,11
component ACIA_Clock
generic (
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
);
port (
clk : in Std_Logic; -- System Clock Input
ACIA_clk : out Std_logic -- ACIA Clock output
ACIA_clk : out Std_logic -- ACIA Clock output
);
end component;
 
515,29 → 515,29
generic(
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
VGA_LIN_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 2; -- LINES
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
VGA_LIN_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 2; -- LINES
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 25MHz
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 25MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
561,9 → 561,9
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
------------------------------------------------------------
573,8 → 573,8
------------------------------------------------------------
 
component trap
port (
clk : in std_logic;
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
581,8 → 581,8
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
595,13 → 595,13
component dat_ram
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_lo : in std_logic_vector(3 downto 0);
addr_hi : in std_logic_vector(3 downto 0);
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_lo : in std_logic_vector(3 downto 0);
addr_hi : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
663,7 → 663,7
component BUFG
Port (
i: in std_logic;
o: out std_logic
o: out std_logic
);
end component;
 
673,25 → 673,25
-----------------------------------------------------------------------------
 
my_cpu : cpu09 port map (
clk => cpu_clk,
clk => cpu_clk,
rst => cpu_reset,
vma => cpu_vma,
addr => cpu_addr(15 downto 0),
rw => cpu_rw,
data_out => cpu_data_out,
rw => cpu_rw,
data_out => cpu_data_out,
data_in => cpu_data_in,
irq => cpu_irq,
firq => cpu_firq,
nmi => cpu_nmi,
halt => cpu_halt,
hold => cpu_hold
irq => cpu_irq,
firq => cpu_firq,
nmi => cpu_nmi,
halt => cpu_halt,
hold => cpu_hold
);
 
my_rom : mon_rom port map (
clk => cpu_clk,
rst => cpu_reset,
cs => rom_cs,
rw => '1',
rst => cpu_reset,
cs => rom_cs,
rw => '1',
addr => cpu_addr(11 downto 0),
data_in => cpu_data_out,
data_out => rom_data_out
700,8 → 700,8
my_flex : flex_ram port map (
clk => cpu_clk,
rst => cpu_reset,
cs => flex_cs,
rw => cpu_rw,
cs => flex_cs,
rw => cpu_rw,
addr => cpu_addr(12 downto 0),
data_out => flex_data_out,
data_in => cpu_data_out
708,28 → 708,28
);
 
my_acia : acia6850 port map (
clk => cpu_clk,
rst => cpu_reset,
clk => cpu_clk,
rst => cpu_reset,
cs => acia_cs,
rw => cpu_rw,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => acia_data_out,
data_in => cpu_data_out,
data_out => acia_data_out,
irq => acia_irq,
RxC => acia_clk,
TxC => acia_clk,
RxD => rxd,
TxD => txd,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
RxC => acia_clk,
TxC => acia_clk,
RxD => rxd,
TxD => txd,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
 
 
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
clk => Clk_i,
743,20 → 743,20
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_CLK_FREQ => CPU_CLK_FREQ
)
KBD_CLK_FREQ => CPU_CLK_FREQ
)
port map(
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => ps2_clk,
kbd_data => ps2_dat
);
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => ps2_clk,
kbd_data => ps2_dat
);
 
----------------------------------------
--
767,30 → 767,30
generic map(
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
VGA_HOR_CHARS => 80, -- CHARACTERS
VGA_VER_CHARS => 25, -- CHARACTERS
VGA_PIX_PER_CHAR => 8, -- PIXELS
VGA_LIN_PER_CHAR => 16, -- LINES
VGA_HOR_BACK_PORCH => 40, -- PIXELS
VGA_HOR_SYNC => 96, -- PIXELS
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
VGA_VER_BACK_PORCH => 13, -- LINES
VGA_VER_SYNC => 2, -- LINES
VGA_VER_FRONT_PORCH => 35 -- LINES
VGA_HOR_CHARS => 80, -- CHARACTERS
VGA_VER_CHARS => 25, -- CHARACTERS
VGA_PIX_PER_CHAR => 8, -- PIXELS
VGA_LIN_PER_CHAR => 16, -- LINES
VGA_HOR_BACK_PORCH => 40, -- PIXELS
VGA_HOR_SYNC => 96, -- PIXELS
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
VGA_VER_BACK_PORCH => 13, -- LINES
VGA_VER_SYNC => 2, -- LINES
VGA_VER_FRONT_PORCH => 35 -- LINES
)
port map(
 
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_reset,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red_o,
vga_green_o => vga_green_o,
vga_blue_o => vga_blue_o,
805,12 → 805,12
----------------------------------------
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_reset,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq
);
 
819,29 → 819,29
-- Bus Trap Interrupt logic
--
----------------------------------------
my_trap : trap port map (
clk => cpu_clk,
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
data_out => trap_data_out,
irq => trap_irq
);
 
 
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
data_out => dat_addr(7 downto 0)
);
 
------------------------------------------------------------------------
-- Instantiate the SDRAM controller that connects to the memory tester
850,9 → 850,9
u1 : xsaSDRAMCntl
generic map(
FREQ => MEM_CLK_FREQ,
CLK_DIV => SYS_CLK_DIV,
CLK_DIV => SYS_CLK_DIV,
PIPE_EN => PIPE_EN,
MAX_NOP => MAX_NOP,
MAX_NOP => MAX_NOP,
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
DATA_WIDTH => DATA_WIDTH,
NROWS => NROWS,
861,7 → 861,7
SADDR_WIDTH => SADDR_WIDTH
)
port map(
-- Host Side
-- Host Side
clk => CLKA, -- master clock from external clock source (unbuffered)
bufclk => open, -- buffered master clock output
clk1x => clk_i, -- synchronized master clock (accounts for delays to external SDRAM)
881,7 → 881,7
hDIn => hDIn, -- test data pattern from memory tester to SDRAM
hDOut => hDOut, -- SDRAM data output to memory tester
status => open, -- SDRAM controller state (for diagnostics)
-- SDRAM Side
-- SDRAM Side
sclkfb => SDRAM_clkfb, -- clock feedback with added external PCB delays
sclk => SDRAM_clkout, -- synchronized clock to external SDRAM
cke => SDRAM_cke, -- SDRAM clock enable
898,14 → 898,14
 
cpu_clk_buffer : BUFG port map(
i => Clk25,
o => cpu_clk
);
o => cpu_clk
);
 
vga_clk_buffer : BUFG port map(
i => Clk25,
o => vga_clk
);
o => vga_clk
);
----------------------------------------------------------------------
--
-- Process to decode memory map
913,169 → 913,169
----------------------------------------------------------------------
 
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
dat_addr,
rom_data_out,
flex_data_out,
acia_data_out,
keyboard_data_out,
vdu_data_out,
pb_data_out,
timer_data_out,
trap_data_out,
ram_data_out
)
dat_addr,
rom_data_out,
flex_data_out,
acia_data_out,
keyboard_data_out,
vdu_data_out,
pb_data_out,
timer_data_out,
trap_data_out,
ram_data_out
)
begin
cpu_data_in <= (others=>'0');
dat_cs <= '0';
rom_cs <= '0';
flex_cs <= '0';
acia_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
pb_cs <= '0';
ide_cs <= '0';
ether_cs <= '0';
slot1_cs <= '0';
slot2_cs <= '0';
ram_cs <= '0';
acia_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
pb_cs <= '0';
ide_cs <= '0';
ether_cs <= '0';
slot1_cs <= '0';
slot2_cs <= '0';
ram_cs <= '0';
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma; -- write DAT
rom_cs <= cpu_vma; -- read ROM
--
-- Sys09Bug Monitor ROM $F000 - $FFFF
--
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma;
--
-- Sys09Bug Monitor ROM $F000 - $FFFF
--
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma;
 
--
-- IO Devices $E000 - $E7FF
--
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
case cpu_addr(11 downto 8) is
--
-- SWTPC peripherals from $E000 to $E0FF
--
when "0000" =>
case cpu_addr(7 downto 4) is
--
-- Console Port ACIA $E000 - $E00F
--
when "0000" => -- $E000
cpu_data_in <= acia_data_out;
acia_cs <= cpu_vma;
-- IO Devices $E000 - $E7FF
--
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
case cpu_addr(11 downto 8) is
--
-- SWTPC peripherals from $E000 to $E0FF
--
when "0000" =>
case cpu_addr(7 downto 4) is
--
-- Console Port ACIA $E000 - $E00F
--
when "0000" => -- $E000
cpu_data_in <= acia_data_out;
acia_cs <= cpu_vma;
 
--
-- Reserved
-- Floppy Disk Controller port $E010 - $E01F
--
-- Floppy Disk Controller port $E010 - $E01F
--
 
--
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
--
when "0010" => -- $E020
cpu_data_in <= keyboard_data_out;
keyboard_cs <= cpu_vma;
keyboard_cs <= cpu_vma;
 
--
-- VDU port $E030 - $E03F
--
when "0011" => -- $E030
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
vdu_cs <= cpu_vma;
vdu_cs <= cpu_vma;
 
--
-- Reserved SWTPc MP-T Timer $E040 - $E04F
--
when "0100" => -- $E040
-- Reserved SWTPc MP-T Timer $E040 - $E04F
--
when "0100" => -- $E040
cpu_data_in <= (others=> '0');
 
--
-- Timer $E050 - $E05F
--
when "0101" => -- $E050
--
when "0101" => -- $E050
cpu_data_in <= timer_data_out;
timer_cs <= cpu_vma;
 
--
-- Bus Trap Logic $E060 - $E06F
--
when "0110" => -- $E060
--
when "0110" => -- $E060
cpu_data_in <= trap_data_out;
trap_cs <= cpu_vma;
trap_cs <= cpu_vma;
 
--
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
--
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
--
 
--
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
--
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
--
 
--
-- Remaining 6 slots reserved for non SWTPc Peripherals
--
when others => -- $E0A0 to $E0FF
null;
end case;
--
-- XST-3.0 Peripheral Bus goes here
-- $E100 to $E1FF
-- Four devices
-- IDE, Ethernet, Slot1, Slot2
--
when "0001" =>
cpu_data_in <= pb_data_out;
pb_cs <= cpu_vma;
case cpu_addr(7 downto 6) is
--
-- IDE Interface $E100 to $E13F
--
when "00" =>
ide_cs <= cpu_vma;
--
-- Ethernet Interface $E140 to $E17F
--
when "01" =>
ether_cs <= cpu_vma;
--
-- Slot 1 Interface $E180 to $E1BF
--
when "10" =>
slot1_cs <= cpu_vma;
--
-- Slot 2 Interface $E1C0 to $E1FF
--
when "11" =>
slot2_cs <= cpu_vma;
--
-- Nothing else
--
-- Remaining 6 slots reserved for non SWTPc Peripherals
--
when others => -- $E0A0 to $E0FF
null;
end case;
--
-- XST-3.0 Peripheral Bus goes here
-- $E100 to $E1FF
-- Four devices
-- IDE, Ethernet, Slot1, Slot2
--
when "0001" =>
cpu_data_in <= pb_data_out;
pb_cs <= cpu_vma;
case cpu_addr(7 downto 6) is
--
-- IDE Interface $E100 to $E13F
--
when "00" =>
ide_cs <= cpu_vma;
--
-- Ethernet Interface $E140 to $E17F
--
when "01" =>
ether_cs <= cpu_vma;
--
-- Slot 1 Interface $E180 to $E1BF
--
when "10" =>
slot1_cs <= cpu_vma;
--
-- Slot 2 Interface $E1C0 to $E1FF
--
when "11" =>
slot2_cs <= cpu_vma;
--
-- Nothing else
--
when others =>
null;
null;
end case;
--
-- $E200 to $EFFF reserved for future use
--
when others =>
null;
-- $E200 to $EFFF reserved for future use
--
when others =>
null;
end case;
--
-- Flex RAM $0C000 - $0DFFF
--
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
cpu_data_in <= flex_data_out;
flex_cs <= cpu_vma;
--
-- Everything else is RAM
--
else
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end if;
--
-- Flex RAM $0C000 - $0DFFF
--
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
cpu_data_in <= flex_data_out;
flex_cs <= cpu_vma;
--
-- Everything else is RAM
--
else
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end if;
end process;
 
 
1103,10 → 1103,10
pb_rreg <= (others => '0');
elsif clk_i'event and clk_i ='1' then
if pb_wru = '1' then
pb_wreg <= cpu_data_out;
pb_wreg <= cpu_data_out;
end if;
if pb_rdu = '1' then
pb_rreg <= pb_d(7 downto 0);
pb_rreg <= pb_d(7 downto 0);
end if;
end if;
--
1118,9 → 1118,9
pb_wr_n <= '1';
pb_rd_n <= '1';
elsif clk_i'event and clk_i ='1' then
if pb_hold = '1' then
pb_wr_n <= not pb_wrl;
pb_rd_n <= not pb_rdu;
if pb_hold = '1' then
pb_wr_n <= not pb_wrl;
pb_rd_n <= not pb_rdu;
else
pb_wr_n <= '1';
pb_rd_n <= '1';
1160,39 → 1160,39
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl ) --, ether_rdy )
begin
if cpu_reset = '1' then
pb_release <= '0';
pb_count <= "0000";
pb_hold_state <= hold_release_state;
elsif rising_edge(cpu_clk) then
pb_release <= '0';
pb_count <= "0000";
pb_hold_state <= hold_release_state;
elsif rising_edge(cpu_clk) then
--
-- The perpheral bus hold signal should be generated on
-- 16 bit bus read which will be on even byte reads or
-- 16 bit bus write which will be on odd byte writes.
--
case pb_hold_state is
when hold_release_state =>
case pb_hold_state is
when hold_release_state =>
pb_release <= '0';
if (pb_rdu = '1') or (pb_wrl = '1') then
pb_count <= "0100";
pb_hold_state <= hold_request_state;
if (pb_rdu = '1') or (pb_wrl = '1') then
pb_count <= "0100";
pb_hold_state <= hold_request_state;
elsif (pb_rdl = '1') or (pb_wru = '1') then
pb_release <= '1';
pb_hold_state <= hold_release_state;
end if;
pb_hold_state <= hold_release_state;
end if;
 
when hold_request_state =>
if pb_count = "0000" then
when hold_request_state =>
if pb_count = "0000" then
-- if ether_rdy = '1' then
pb_release <= '1';
pb_hold_state <= hold_release_state;
pb_hold_state <= hold_release_state;
-- end if;
else
pb_count <= pb_count - "0001";
end if;
pb_count <= pb_count - "0001";
end if;
when others =>
null;
null;
end case;
end if;
end if;
end process;
 
--
1200,9 → 1200,9
--
compact_flash: process( ide_cs, cpu_addr )
begin
ide_cs0_n <= not( ide_cs ) or cpu_addr(4);
ide_cs1_n <= not( ide_cs and cpu_addr(4));
ide_dmack_n <= '1';
ide_cs0_n <= not( ide_cs ) or cpu_addr(4);
ide_cs1_n <= not( ide_cs and cpu_addr(4));
ide_dmack_n <= '1';
end process;
 
--
1209,20 → 1209,20
-- Interrupts and other bus control signals
--
interrupts : process( SW3_N,
pb_cs, pb_hold, pb_release, ram_hold,
-- ether_irq,
pb_cs, pb_hold, pb_release, ram_hold,
-- ether_irq,
acia_irq,
keyboard_irq,
trap_irq,
timer_irq
)
keyboard_irq,
trap_irq,
timer_irq
)
begin
pb_hold <= pb_cs and (not pb_release);
cpu_irq <= acia_irq or keyboard_irq;
cpu_nmi <= trap_irq or not( SW3_N );
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= pb_hold or ram_hold;
cpu_nmi <= trap_irq or not( SW3_N );
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= pb_hold or ram_hold;
FLASH_CE_N <= '1';
end process;
 
1233,11 → 1233,11
my_led_flasher: process( clk_i, rst_i, CountL )
begin
if rst_i = '1' then
CountL <= "000000000000000000000000";
CountL <= "000000000000000000000000";
elsif rising_edge(clk_i) then
CountL <= CountL + 1;
CountL <= CountL + 1;
end if;
-- S(7 downto 0) <= CountL(23 downto 16);
-- S(7 downto 0) <= CountL(23 downto 16);
end process;
 
--
1248,15 → 1248,15
if rising_edge( clk_i ) then
 
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
end if;
 
if clk_count = 0 then
clk25 <= '0';
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
clk25 <= '1';
end if;
 
end if;
1323,62 → 1323,62
--
my_sdram_rw : process( clk_i, cpu_reset,
opBegun, ramDone,
ram_state,
ram_state,
ram_rd_req, ram_wr_req )
begin
if( cpu_reset = '1' ) then
hRd <= '0';
hRd <= '0';
hWr <= '0';
ram_hold <= '0';
ram_state <= ram_state_0;
ram_hold <= '0';
ram_state <= ram_state_0;
 
elsif( falling_edge(clk_i) ) then
--
-- ram state machine
--
-- ram state machine
--
case ram_state is
 
when ram_state_0 =>
if ram_rd_req = '1' then
if ram_rd_req = '1' then
ram_hold <= '1';
hRd <= '1';
ram_state <= ram_state_rd1;
hRd <= '1';
ram_state <= ram_state_rd1;
elsif ram_wr_req = '1' then
ram_hold <= '1';
ram_hold <= '1';
hWr <= '1';
ram_state <= ram_state_wr1;
ram_state <= ram_state_wr1;
end if;
 
when ram_state_rd1 =>
if opBegun = '1' then
hRd <= '0';
ram_state <= ram_state_rd2;
if opBegun = '1' then
hRd <= '0';
ram_state <= ram_state_rd2;
end if;
 
when ram_state_rd2 =>
if ramDone = '1' then
ram_hold <= '0';
ram_state <= ram_state_3;
end if;
if ramDone = '1' then
ram_hold <= '0';
ram_state <= ram_state_3;
end if;
 
when ram_state_wr1 =>
if opBegun = '1' then
ram_hold <= '0';
hWr <= '0';
ram_state <= ram_state_3;
if opBegun = '1' then
ram_hold <= '0';
hWr <= '0';
ram_state <= ram_state_3;
end if;
 
when ram_state_3 =>
if ram_release = '1' then
ram_state <= ram_state_0;
if ram_release = '1' then
ram_state <= ram_state_0;
end if;
 
when others =>
hRd <= '0';
hWr <= '0';
ram_hold <= '0';
ram_state <= ram_state_0;
end case;
when others =>
hRd <= '0';
hWr <= '0';
ram_hold <= '0';
ram_state <= ram_state_0;
end case;
 
end if;
end process;
1411,10 → 1411,10
ram_bus_hold: process( cpu_clk, cpu_reset, ram_hold )
begin
if ram_hold = '1' then
ram_release <= '0';
elsif falling_edge(cpu_clk) then
ram_release <= '1';
end if;
ram_release <= '0';
elsif falling_edge(cpu_clk) then
ram_release <= '1';
end if;
end process;
 
--
1422,13 → 1422,13
--
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
begin
if hRd = '1' then
ram_rd_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
ram_rd_req <= '1';
if hRd = '1' then
ram_rd_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
ram_rd_req <= '1';
end if;
end if;
end if;
end process;
 
--
1437,12 → 1437,12
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
begin
if hWr = '1' then
ram_wr_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
ram_wr_req <= '1';
ram_wr_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
ram_wr_req <= '1';
end if;
end if;
end if;
end process;
 
 
1450,10 → 1450,10
status_leds : process( rst_i, cpu_reset, lock )
begin
S(0) <= rst_i;
S(1) <= cpu_reset;
S(2) <= lock;
S(3) <= countL(23);
S(7 downto 4) <= "0000";
S(1) <= cpu_reset;
S(2) <= lock;
S(3) <= countL(23);
S(7 downto 4) <= "0000";
end process;
 
--debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,

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