Subversion Repositories System09

System09_Trenz_TE0141/an601.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: System09_Trenz_TE0141/System09_Trenz_TE0141.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: System09_Trenz_TE0141/System09_Trenz_TE0141.ise =================================================================== --- System09_Trenz_TE0141/System09_Trenz_TE0141.ise (nonexistent) +++ System09_Trenz_TE0141/System09_Trenz_TE0141.ise (revision 105)

System09_Trenz_TE0141/System09_Trenz_TE0141.ise Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: System09_Trenz_TE0141/System09_Trenz_TE0141.vhd =================================================================== --- System09_Trenz_TE0141/System09_Trenz_TE0141.vhd (nonexistent) +++ System09_Trenz_TE0141/System09_Trenz_TE0141.vhd (revision 105) @@ -0,0 +1,1169 @@ +-- SECD Front End Processor derived from System09 written by John E. Kent +-- This core adheres to the GNU public license + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; +--use config.all; + +entity System09_trenz is + port( + -- the following output assignments are required so that + -- the GT3200 USB phy generates a 30 MHz clock + utmi_databus16_8 : out std_logic; + utmi_reset : out std_logic; + utmi_xcvrselect : out std_logic; + utmi_termselect : out std_logic; + utmi_opmode1 : out std_logic; + utmi_txvalid : out std_logic; + + -- this is the 30 MHz clock input (clkout is the utmi name) + utmi_clkout : in std_logic; + + reset_sw : in Std_logic; -- Master Reset input (active low) + + -- PS/2 Keyboard + ps2_clk1 : inout Std_logic; + ps2_data1 : inout Std_Logic; + + -- acia Interface + fpga_rxd : in Std_Logic; + fpga_txd : out Std_Logic; + fpga_cts : in Std_Logic; + fpga_rts : out Std_Logic; + + -- CRTC output signals + vsync_b : out Std_Logic; + hsync_b : out Std_Logic; + fpga_b : out Std_Logic_Vector(2 downto 0); + fpga_g : out Std_Logic_Vector(2 downto 0); + fpga_r : out Std_Logic_Vector(2 downto 0); + + -- LEDS & Switches + mm_led : out Std_Logic; + led : out Std_Logic_Vector(3 downto 0); + + joy_down : in Std_Logic; + joy_fire : in Std_Logic; + joy_left : in Std_Logic; + joy_right : in Std_Logic; + joy_up : in Std_Logic; + + -- LCD Display + lcd_e : out Std_Logic; + lcd_rw : out Std_Logic; + lcd_rs : out Std_Logic; + lcd_d : inout Std_Logic_Vector(3 downto 0); + + -- Audio + aud_out : out std_logic_vector(4 downto 1); + + --ir remote control + ir_data : in std_logic; + + -- Memory interface + ram_a : out std_logic_vector(20 downto 0); + ram_io : inout std_logic_vector(15 downto 0); + ram_bhen : out std_logic; + ram_blen : out std_logic; + ram_cen : out std_logic; + ram_oen : out std_logic; + ram_wen : out std_logic; + + -- Flash interface + fl_resetn : out std_logic; + fl_cen : out std_logic; + fl_oen : out std_logic; + fl_byten : out std_logic; + fl_busyn : in std_logic; + + -- Compact flash + cf_we : out std_logic; -- all these signals are active low + cf_reg : out std_logic; -- for more details see the specification + cf_cs0 : out std_logic; -- of compact flash + cf_cs1 : out std_logic; + cf_reset : out std_logic; + cf_iord : out std_logic; + cf_iowr : out std_logic; + cf_irq : in std_logic; + cf_wait : in std_logic; + cf_cd1 : in std_logic; + cf_cd2 : in std_logic; + iois16 : in std_logic; + cf_oe : out std_logic; + cf_dasp : inout std_logic; + cf_pdiag : inout std_logic; + + --cf power enable (active low) + cf_pwr_en : out std_logic + ); +end System09_trenz; + +------------------------------------------------------------------------------- +-- Architecture for System09 +------------------------------------------------------------------------------- +architecture rtl of System09_trenz is + ----------------------------------------------------------------------------- + -- constants + ----------------------------------------------------------------------------- + constant SYS_Clock_Frequency : integer := 50_000_000; -- FPGA System Clock + constant VGA_Clock_Frequency : integer := 25_000_000; -- VGA Pixel Clock + constant CPU_Clock_Frequency : integer := 25_000_000; -- CPU Clock + constant BAUD_Rate : integer := 57600; -- Baud Rate + constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16; + + type hold_state_type is ( hold_release_state, hold_request_state ); + + ----------------------------------------------------------------------------- + -- ChipScope Pro components and signals + ----------------------------------------------------------------------------- + +-- component icon +-- port(control0 : out std_logic_vector(35 downto 0)); +-- end component; + +-- component ila +-- port(control : in std_logic_vector(35 downto 0); +-- clk : in std_logic; +-- trig0 : in std_logic_vector(39 downto 0)); +-- end component; + +-- signal chipscope_control : std_logic_vector(35 downto 0); +-- signal ila_clock : std_logic; + + ----------------------------------------------------------------------------- + -- Signals + ----------------------------------------------------------------------------- + + -- Clocks + attribute buffer_type : string; + attribute period : string; + + signal sys_clk : std_logic; -- 50 Mhz + attribute period of sys_clk : signal is "20 ns"; + attribute buffer_type of sys_clk : signal is "BUFG"; + + signal cpu_clk : std_logic; -- 25 Mhz + attribute period of cpu_clk : signal is "40 ns"; + attribute buffer_type of cpu_clk : signal is "BUFG"; + + signal vga_clk : std_logic; -- 25 Mhz + attribute period of vga_clk : signal is "40 ns"; + attribute buffer_type of vga_clk : signal is "BUFG"; + + -- System Reset (generated by key press) + signal cpu_reset : std_logic; + + -- Dynamic Address Translation + signal dat_cs : std_logic; + signal dat_addr : std_logic_vector(7 downto 0); + + -- BOOT ROM + signal rom_cs : Std_logic; + signal rom_data_out : Std_Logic_Vector(7 downto 0); + + -- FLEX9 RAM + signal flex_cs : Std_logic; + signal flex_data_out : Std_Logic_Vector(7 downto 0); + + -- acia Interface signals + signal acia_data_out : Std_Logic_Vector(7 downto 0); + signal acia_cs : Std_Logic; + signal acia_irq : Std_Logic; + signal baudclk : Std_Logic; + signal DCD_n : Std_Logic; + signal RTS_n : Std_Logic; + signal CTS_n : Std_Logic; + + -- keyboard port + signal keyboard_data_out : std_logic_vector(7 downto 0); + signal keyboard_cs : std_logic; + signal keyboard_irq : std_logic; + + -- CPU Interface signals + signal cpu_rw : std_logic; + signal cpu_vma : std_logic; + signal cpu_halt : std_logic; + signal cpu_hold : std_logic; + signal cpu_firq : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + + -- Compact Flash port + -- CF data bus shared with RAM +-- signal cf_data_out : std_logic_vector(7 downto 0); + signal cf_cs0x : std_logic; + signal cf_cs1x : std_logic; + signal cf_rd : std_logic; + signal cf_wr : std_logic; + signal cf_hold : std_logic; + signal cf_release : std_logic; + signal cf_count : std_logic_vector(3 downto 0); + signal cf_hold_state : hold_state_type; + + -- Video Display Unit + signal vdu_cs : std_logic; + signal vdu_data_out : std_logic_vector(7 downto 0); + + -- VGA output signals (distributed to VGA DAC) + signal red : std_logic; + signal green : std_logic; + signal blue : std_logic; + + -- LCD register select + signal lcd_cs : std_logic; + signal lcd_data_in : std_logic_vector(7 downto 0); + signal lcd_data_out : std_logic_vector(7 downto 0); + + -- LED register select + signal leds_cs : std_logic; + signal leds_data_in : std_logic_vector(7 downto 0) := (others => '0'); + signal leds_data_out : std_logic_vector(7 downto 0) := (others => '0'); + + -- Joystick buffer + signal joy_cs : std_logic; + signal joy_data_out : std_logic_vector(7 downto 0); + + -- External RAM interface + signal ram_cs : std_logic := '0'; + signal ram_data_out : std_logic_vector(7 downto 0); + signal ram_oe : std_logic; + signal ram_we : std_logic; + + -- Locked signal of clock synthesizer + signal clock_locked : std_logic; + signal ila_clock : std_logic; + + -- LED Flasher + signal blink_count : std_logic_vector(25 downto 0) := (others => '0'); + + -- System Clock Prescaler + signal clk_count : std_logic; + + +----------------------------------------------------------------- +-- +-- CPU09 CPU core +-- +----------------------------------------------------------------- + + component cpu09 + port ( + clk : in std_logic; + rst : in std_logic; + rw : out std_logic; -- Asynchronous memory interface + vma : out std_logic; + address : out std_logic_vector(15 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + halt : in std_logic; + hold : in std_logic; + irq : in std_logic; + nmi : in std_logic; + firq : in std_logic + ); + end component; + + +---------------------------------------- +-- +-- 4KByte Block RAM Monitor ROM +-- +---------------------------------------- +component mon_rom + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (11 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); +end component; + +---------------------------------------- +-- +-- 8KBytes Block RAM for FLEX9 +-- $C000 - $DFFF +-- +---------------------------------------- +component flex_ram + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (12 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); +end component; + +---------------------------------------- +-- +-- Dynamic Address Translation Registers +-- +---------------------------------------- +component dat_ram + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr_lo : in std_logic_vector(3 downto 0); + addr_hi : in std_logic_vector(3 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0) + ); +end component; + + +----------------------------------------------------------------- +-- +-- 6850 ACIA / UART +-- +----------------------------------------------------------------- + + component ACIA_6850 + port ( + clk : in Std_Logic; -- System Clock + rst : in Std_Logic; -- Reset input (active high) + cs : in Std_Logic; -- ACIA Chip Select + rw : in Std_Logic; -- Read / Not Write + irq : out Std_Logic; -- Interrupt + Addr : in Std_Logic; -- Register Select + DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In + DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out + RxC : in Std_Logic; -- Receive Baud Clock + TxC : in Std_Logic; -- Transmit Baud Clock + RxD : in Std_Logic; -- Receive Data + TxD : out Std_Logic; -- Transmit Data + DCD_n : in Std_Logic; -- Data Carrier Detect + CTS_n : in Std_Logic; -- Clear To Send + RTS_n : out Std_Logic -- Request To send + ); + end component; + +----------------------------------------------------------------- +-- +-- ACIA Clock divider +-- +----------------------------------------------------------------- + + component ACIA_Clock + generic ( + SYS_Clock_Frequency : integer := SYS_Clock_Frequency; + ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency + ); + port ( + clk : in Std_Logic; -- System Clock Input + ACIA_clk : out Std_logic -- ACIA Clock output + ); + end component; + + +---------------------------------------- +-- +-- PS/2 Keyboard +-- +---------------------------------------- + + component keyboard + generic( + KBD_Clock_Frequency : integer := CPU_Clock_Frequency + ); + port( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic + ); + end component; + +---------------------------------------- +-- +-- Video Display Unit. +-- +---------------------------------------- + component vdu8 + generic( + VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ + VGA_CLOCK_FREQUENCY : integer := VGA_Clock_Frequency; -- HZ + VGA_HOR_CHARS : integer := 80; -- CHARACTERS + VGA_VER_CHARS : integer := 25; -- CHARACTERS + VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS + VGA_LINES_PER_CHAR : integer := 16; -- LINES + VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS + VGA_HOR_SYNC : integer := 96; -- PIXELS + VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS + VGA_VER_BACK_PORCH : integer := 13; -- LINES + VGA_VER_SYNC : integer := 1; -- LINES + VGA_VER_FRONT_PORCH : integer := 36 -- LINES + ); + port( + -- control register interface + vdu_clk : in std_logic; -- CPU Clock - 12.5MHz + vdu_rst : in std_logic; + vdu_cs : in std_logic; + vdu_rw : in std_logic; + vdu_addr : in std_logic_vector(2 downto 0); + vdu_data_in : in std_logic_vector(7 downto 0); + vdu_data_out : out std_logic_vector(7 downto 0); + + -- vga port connections + vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz + vga_red_o : out std_logic; + vga_green_o : out std_logic; + vga_blue_o : out std_logic; + vga_hsync_o : out std_logic; + vga_vsync_o : out std_logic + ); + end component; + +-- component ram_controller +-- port( +-- reset : in std_logic; +-- clk : in std_logic; +-- cs_ram : in std_logic; +-- rw : in std_logic; +-- din : in std_logic_vector(7 downto 0); +-- dout : out std_logic_vector(7 downto 0); +-- addr : in std_logic_vector(19 downto 0); + + -- External interface +-- ram_oen : out std_logic; +-- ram_cen : out std_logic; +-- ram_wen : out std_logic; +-- ram_io : inout std_logic_vector(15 downto 0); +-- ram_a : out std_logic_vector(20 downto 1); +-- ram_bhen : out std_logic; +-- ram_blen : out std_logic +-- ); +-- end component; + +component BUFG + port ( + i : in std_logic; + o : out std_logic + ); +end component; + +begin + + ----------------------------------------------------------------- + -- + -- ChipsScope Pro cores + -- + ----------------------------------------------------------------- + +-- i_icon : icon +-- port map(control0 => chipscope_control); +-- +-- i_ila : ila +-- port map(control => chipscope_control, +-- clk => ila_clock, +-- trig0(15 downto 8) => cpu_data_in, +-- trig0(23 downto 16) => cpu_data_out, +-- trig0(39 downto 24) => cpu_addr, +-- trig0(0) => cpu_clk, +-- trig0(1) => cpu_vma, +-- trig0(2) => ram_bhenx, +-- trig0(3) => ram_blenx, +-- trig0(4) => ram_cenx, +-- trig0(5) => ram_oenx, +-- trig0(6) => ram_wenx, +-- trig0(7) => vga_clk); + + + + ----------------------------------------------------------------- + -- + -- CPU09 CPU core + -- + ----------------------------------------------------------------- + + my_cpu : entity cpu09 port map ( + clk => cpu_clk, + rst => cpu_reset, + rw => cpu_rw, + vma => cpu_vma, + address => cpu_addr, + data_in => cpu_data_in, + data_out => cpu_data_out, + halt => cpu_halt, + hold => cpu_hold, + irq => cpu_irq, + nmi => cpu_nmi, + firq => cpu_firq + ); + + ---------------------------------------- + -- + -- Sys09Bug ROM (Xilinx Block RAM, 4k) + -- + ---------------------------------------- + +my_rom : mon_rom port map ( + clk => cpu_clk, + rst => cpu_reset, + cs => rom_cs, + rw => '1', + addr => cpu_addr(11 downto 0), + rdata => rom_data_out, + wdata => cpu_data_out + ); + + ---------------------------------------- + -- + -- Flex Operating System (Xilinx Block RAM, 8k) + -- + ---------------------------------------- + +my_flex : flex_ram port map ( + clk => cpu_clk, + rst => cpu_reset, + cs => flex_cs, + rw => cpu_rw, + addr => cpu_addr(12 downto 0), + rdata => flex_data_out, + wdata => cpu_data_out + ); + + ---------------------------------------- + -- + -- Dynamic Address Translation + -- + ---------------------------------------- + +my_dat : dat_ram port map ( + clk => cpu_clk, + rst => cpu_reset, + cs => dat_cs, + rw => cpu_rw, + addr_hi => cpu_addr(15 downto 12), + addr_lo => cpu_addr(3 downto 0), + data_in => cpu_data_out, + data_out => dat_addr(7 downto 0) + ); + + + ----------------------------------------------------------------- + -- + -- 6850 ACIA + -- + ----------------------------------------------------------------- + + my_acia : entity acia_6850 port map ( + clk => cpu_clk, + rst => cpu_reset, + cs => acia_cs, + rw => cpu_rw, + irq => acia_irq, + Addr => cpu_addr(0), + Datain => cpu_data_out, + DataOut => acia_data_out, + RxC => baudclk, + TxC => baudclk, + RxD => fpga_rxd, + TxD => fpga_txd, + DCD_n => dcd_n, + CTS_n => fpga_cts, + RTS_n => fpga_rts + ); + + +---------------------------------------- +-- +-- PS/2 Keyboard Interface +-- +---------------------------------------- + my_keyboard : keyboard + generic map ( + KBD_Clock_Frequency => CPU_Clock_frequency + ) + port map( + clk => cpu_clk, + rst => cpu_reset, + cs => keyboard_cs, + rw => cpu_rw, + addr => cpu_addr(0), + data_in => cpu_data_out(7 downto 0), + data_out => keyboard_data_out(7 downto 0), + irq => keyboard_irq, + kbd_clk => ps2_clk1, + kbd_data => ps2_data1 + ); + +---------------------------------------- +-- +-- Video Display Unit instantiation +-- +---------------------------------------- + my_vdu : vdu8 + generic map( + VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ + VGA_CLOCK_FREQUENCY => VGA_Clock_Frequency, -- HZ + VGA_HOR_CHARS => 80, -- CHARACTERS + VGA_VER_CHARS => 25, -- CHARACTERS + VGA_PIXELS_PER_CHAR => 8, -- PIXELS + VGA_LINES_PER_CHAR => 16, -- LINES + VGA_HOR_BACK_PORCH => 40, -- PIXELS + VGA_HOR_SYNC => 96, -- PIXELS + VGA_HOR_FRONT_PORCH => 24, -- PIXELS + VGA_VER_BACK_PORCH => 13, -- LINES + VGA_VER_SYNC => 1, -- LINES + VGA_VER_FRONT_PORCH => 36 -- LINES + ) + port map( + + -- Control Registers + vdu_clk => cpu_clk, -- 12.5 MHz System Clock in + vdu_rst => cpu_reset, + vdu_cs => vdu_cs, + vdu_rw => cpu_rw, + vdu_addr => cpu_addr(2 downto 0), + vdu_data_in => cpu_data_out, + vdu_data_out => vdu_data_out, + + -- vga port connections + vga_clk => vga_clk, -- 25 MHz VDU pixel clock + vga_red_o => red, + vga_green_o => green, + vga_blue_o => blue, + vga_hsync_o => hsync_b, + vga_vsync_o => vsync_b + ); + + ---------------------------------------- + -- + -- Clock Synthesis instantiation + -- + ---------------------------------------- + + my_clock_synthesis : entity clock_synthesis port map ( + clk_30mhz => utmi_clkout, + sys_clk_out => sys_clk, + locked => clock_locked ); + + +vga_clk_buffer : BUFG port map( + i => clk_count, + o => vga_clk + ); + +cpu_clk_buffer : BUFG port map( + i => clk_count, + o => cpu_clk + ); + + ---------------------------------------- + -- + -- RAM Controller instantiation + -- + ---------------------------------------- + +-- my_external_ram : entity ram_controller port map ( +-- reset => cpu_reset, +-- clk => cpu_clk, +-- cs_ram => ram_cs, +-- rw => cpu_rw, +-- din => cpu_data_out, +-- dout => ram_data_out, +-- addr(19 downto 12) => dat_addr( 7 downto 0), +-- addr(11 downto 0) => cpu_addr(11 downto 0), + + -- external interface +-- ram_oen => ram_oenx, +-- ram_cen => ram_cenx, +-- ram_wen => ram_wenx, +-- ram_io => ram_io, +-- ram_a => ram_a, +-- ram_bhen => ram_bhenx, +-- ram_blen => ram_blenx +-- ); + + +---------------------------------------- +-- +-- ACIA Clock +-- +---------------------------------------- + my_ACIA_Clock : ACIA_Clock + generic map( + SYS_Clock_Frequency => SYS_Clock_Frequency, + ACIA_Clock_Frequency => ACIA_Clock_Frequency + ) + port map( + clk => sys_clk, + acia_clk => baudclk + ); + + +-- +-- Generate a 25 MHz Clock from 50 MHz +-- +my_sys09_clk : process( sys_clk, clk_count ) +begin + if sys_clk'event and sys_clk = '1' then + clk_count <= not clk_count; + end if; +end process; + +---------------------------------------------------------------------- +-- +-- Process to decode memory map +-- +---------------------------------------------------------------------- + +mem_decode: process( cpu_addr, cpu_rw, cpu_vma, + dat_cs, dat_addr, + rom_data_out, + acia_data_out, + keyboard_data_out, + vdu_data_out, + joy_data_out, + lcd_data_out, + leds_data_out, + flex_data_out, + ram_data_out + ) +begin + cpu_data_in <= (others => '0'); + dat_cs <= '0'; + rom_cs <= '0'; + acia_cs <= '0'; + keyboard_cs <= '0'; + vdu_cs <= '0'; + cf_cs0x <= '0'; + cf_cs1x <= '0'; + joy_cs <= '0'; + lcd_cs <= '0'; + leds_cs <= '0'; + flex_cs <= '0'; + ram_cs <= '0'; + + if cpu_addr( 15 downto 8 ) = "11111111" then + cpu_data_in <= rom_data_out; + dat_cs <= cpu_vma; -- write DAT + rom_cs <= cpu_vma; -- read ROM + -- + -- Sys09Bug Monitor ROM $F000 - $FFFF + -- + elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF + -- + -- Monitor ROM $F000 - $FFFF + -- + cpu_data_in <= rom_data_out; + rom_cs <= cpu_vma; -- read ROM + + -- + -- IO Devices $E000 - $EFFF + -- + elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF + dat_cs <= '0'; + rom_cs <= '0'; + case cpu_addr(11 downto 8) is + when "0000" => + case cpu_addr(7 downto 4) is + -- + -- UART / ACIA ($E000 - $E00F) + -- + when "0000" => + cpu_data_in <= acia_data_out; + acia_cs <= cpu_vma; + + -- + -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC) + -- + + -- + -- Keyboard port ($E020 - $E02F) + -- + when "0010" => + cpu_data_in <= keyboard_data_out; + keyboard_cs <= cpu_vma; + + -- + -- VDU port ($E030 - $E03F) + -- + when "0011" => + cpu_data_in <= vdu_data_out; + vdu_cs <= cpu_vma; + + -- + -- Reserved SWTPc MP-T ($E040 - $E04F) + -- + + -- + -- Reserved - Timer ($E050 - $E05F) (B5-X300) + -- + + -- + -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300) + -- + + -- + -- Reserved - I/O port ($E070 - $E07F) (B5-X300) + -- + + -- + -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC) + -- + + -- + -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC) + -- + + -- + -- Read LED port ($E0A0 - $E0AF) + -- Write LEDS + -- + when "1010" => + cpu_data_in <= leds_data_out; + leds_cs <= cpu_vma; + + -- + -- LCD display port ($E0B0 - $E0BF) + -- + when "1011" => + cpu_data_in <= lcd_data_out; + lcd_cs <= cpu_vma; + + -- + -- Read Joy Stick port ($E0D0 - $E0DF) + -- Write LEDS + -- + when "1101" => + cpu_data_in <= joy_data_out; + joy_cs <= cpu_vma; + + -- + -- Read LED port ($E0E0 - $E0EF) + -- Write LEDS + -- + when "1110" => + cpu_data_in <= leds_data_out; + leds_cs <= cpu_vma; + + -- + -- LCD display port ($E0F0 - $E0BF) + -- + when "1111" => + cpu_data_in <= lcd_data_out; + lcd_cs <= cpu_vma; + + when others => -- $EXC0 to $EXFF + null; + + end case; + -- + -- XST-3.0 Peripheral Bus goes here + -- $E100 to $E1FF + -- Four devices + -- IDE, Ethernet, Slot1, Slot2 + -- + when "0001" => + cpu_data_in <= ram_data_out; + + case cpu_addr(7 downto 4) is + -- + -- CF Interface $E100 to $E1FF + -- + when "0000" => + cf_cs0x <= cpu_vma; + + when "0001" => + cf_cs1x <= cpu_vma; + -- + -- Nothing else + -- + when others => + null; + end case; + -- + -- $E200 to $EFFF reserved for future use + -- + when others => + cpu_data_in <= (others => '0'); + end case; + -- + -- FLEX RAM $0C000 - $0DFFF + -- + elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF + cpu_data_in <= flex_data_out; + flex_cs <= cpu_vma; + -- + -- Everything else is RAM + -- + else + cpu_data_in <= ram_data_out; + ram_cs <= cpu_vma; + end if; +end process; + +-- +-- 1M byte SRAM Control +-- Processes to read and write memory based on bus signals +-- using bhe/ble controlled read and write. +-- Can't gate the write pulse with the clock +-- because the bus is shared with the CF +-- which uses clock stretching. +-- +ram_process: process( cpu_reset, sys_clk, cpu_addr, cpu_rw, cpu_data_out, dat_addr, + ram_cs, ram_io, ram_we, ram_oe ) +begin + -- + -- ram_hold signal helps + -- + if( cpu_reset = '1' ) then + ram_we <= '0'; + ram_oe <= '0'; + -- + -- Clock Hold on rising edge + -- + elsif( sys_clk'event and sys_clk='1' ) then + if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then + ram_we <= not cpu_rw; + ram_oe <= cpu_rw; + else + ram_we <= '0'; + ram_oe <= '0'; + end if; + end if; + + ram_cen <= not ram_cs; + ram_bhen <= cpu_addr(0); + ram_blen <= not cpu_addr(0); + ram_wen <= not ram_we; + ram_oen <= not ram_oe; + + ram_a(20) <= '0'; + ram_a(19 downto 0) <= dat_addr(7 downto 0) & cpu_addr(11 downto 0); + + if (cpu_rw = '0') and (cpu_addr(0) = '0') then + ram_io(15 downto 8) <= cpu_data_out; + else + ram_io(15 downto 8) <= "ZZZZZZZZ"; + end if; + + if (cpu_rw = '0') and (cpu_addr(0) = '1') then + ram_io(7 downto 0) <= cpu_data_out; + else + ram_io(7 downto 0) <= "ZZZZZZZZ"; + end if; + + if cpu_addr(0) = '0' then + ram_data_out <= ram_io(15 downto 8); + else + ram_data_out <= ram_io(7 downto 0); + end if; +end process; + +-- +-- Compact Flash Control +-- Configure compact flash for TRUE IDE mode +-- + compact_flash: process( reset_sw, + cpu_addr, cpu_rw, cpu_vma, cpu_data_out, + cf_cs0x, cf_cs1x, cf_rd, cf_wr, cf_cd1, cf_cd2 ) + begin + cf_reset <= reset_sw; + cf_pwr_en <= (cf_cd1) or (cf_cd2); -- power enable when card detect + cf_oe <= '0'; -- TRUE IDE mode + cf_we <= '1'; + cf_reg <= '1'; + cf_cs0 <= not cf_cs0x; + cf_cs1 <= not cf_cs1x; + cf_wr <= (cf_cs0x or cf_cs1x) and (not cpu_rw); + cf_rd <= (cf_cs0x or cf_cs1x) and cpu_rw; + cf_iowr <= not cf_wr; + cf_iord <= not cf_rd; + end process; + + +-- +-- Hold CF access for a few cycles +-- +cf_hold_proc: process( cpu_clk, cpu_reset ) +begin + if cpu_reset = '1' then + cf_release <= '0'; + cf_count <= "0000"; + cf_hold_state <= hold_release_state; + elsif falling_edge( cpu_clk ) then + case cf_hold_state is + when hold_release_state => + cf_release <= '0'; + if (cf_cs0x = '1') or (cf_cs1x = '1') then + cf_count <= "0011"; + cf_hold_state <= hold_request_state; + end if; + + when hold_request_state => + cf_count <= cf_count - "0001"; + if cf_count = "0000" then + cf_release <= '1'; + cf_hold_state <= hold_release_state; + end if; + when others => + null; + end case; + end if; + +end process; + + +-- +-- Interrupts and other bus control signals +-- + interrupts : process( acia_irq, keyboard_irq, joy_up, cf_cs0x, cf_cs1x, cf_hold, cf_release ) + begin + cf_hold <= (cf_cs0x or cf_cs1x) and (not cf_release); + cpu_irq <= keyboard_irq; + cpu_nmi <= not joy_up; + cpu_firq <= acia_irq; + cpu_halt <= '0'; + cpu_hold <= cf_hold; + end process; + + -- + -- LCD write register + -- LCD_data_in and LCD_data_out + -- are relative to the CPU + -- Not the LCD display + -- + lcd_control : process(cpu_reset, cpu_clk, lcd_data_in, lcd_d ) + begin + if cpu_reset = '1' then + lcd_data_in <= (others => '0'); + elsif falling_edge(cpu_clk) then + if lcd_cs = '1' and cpu_rw = '0' then + lcd_data_in <= cpu_data_out; + end if; + end if; + if lcd_data_in(4) = '1' and lcd_data_in(5) = '0' then + lcd_d <= lcd_data_in(3 downto 0); + else + lcd_d <= (others => 'Z'); + end if; + lcd_e <= lcd_data_in(4); + lcd_rw <= lcd_data_in(5); + lcd_rs <= lcd_data_in(6); + -- read back control signals + lcd_data_out(7 downto 4) <= lcd_data_in(7 downto 4); + -- read back 4 bit data bus + lcd_data_out(3 downto 0) <= lcd_d(3 downto 0); + end process; + + -- + -- LED write register + -- + led_control : process(cpu_reset, cpu_clk, leds_data_in) + begin + if cpu_reset = '1' then + leds_data_in <= (others => '1'); + elsif falling_edge(cpu_clk) then + if leds_cs = '1' and cpu_rw = '0' then + leds_data_in <= cpu_data_out; + end if; + end if; + led <= leds_data_in(3 downto 0); + -- read back output state + leds_data_out <= leds_data_in; + end process; + + + -- + -- Joystick register + -- + read_joystick : process(cpu_clk, joy_up, joy_right, joy_down, joy_left, joy_fire) + begin + if rising_edge(cpu_clk) then + joy_data_out(0) <= joy_up; + joy_data_out(1) <= joy_right; + joy_data_out(2) <= joy_down; + joy_data_out(3) <= joy_left; + joy_data_out(4) <= joy_fire; + joy_data_out(7 downto 5) <= (others => '0'); + end if; + end process; + +-- +-- LED Flasher +-- + my_led_flasher: process(vga_clk, cpu_reset, blink_count) + begin + if cpu_reset = '1' then + blink_count <= (others => '0'); + elsif rising_edge(vga_clk) then + blink_count <= blink_count + 1; + end if; + + mm_led <= blink_count(25); + + end process; + + +-- Set acia DCD to always true + DCD_n <= '0'; + +-- +-- configure utmi for 30MHz clock +-- + utmi_databus16_8 <= '1'; + utmi_reset <= '0'; + utmi_xcvrselect <= '1'; + utmi_termselect <= '1'; + utmi_opmode1 <= '0'; + utmi_txvalid <= '0'; + +-- +-- Feed RGB DAC +-- + fpga_r(0) <= red; + fpga_r(1) <= red; + fpga_r(2) <= red; + fpga_g(0) <= green; + fpga_g(1) <= green; + fpga_g(2) <= green; + fpga_b(0) <= blue; + fpga_b(1) <= blue; + fpga_b(2) <= blue; + + -- Hold system in reset until the clock is locked or when the reset + -- key is pressed. + cpu_reset <= (not reset_sw ) or (not clock_locked); + + -- + -- Terminate Audio Output signals + -- + aud_out <= (others => '0'); + + -- + -- Terminate Flash memory controls + -- + fl_resetn <= '1'; + fl_cen <= '1'; + fl_oen <= '1'; + fl_byten <= '1'; + +-- debug output +-- input detected from an IR remote control is forwarded to the LED on the micromodule. +-- there it is easily accessible by a scope and you can also see some flicker when pressing a button. +-- mm_led <= ir_data; + + +end; + Index: System09_Trenz_TE0141/secd_ram_controller.vhd =================================================================== --- System09_Trenz_TE0141/secd_ram_controller.vhd (nonexistent) +++ System09_Trenz_TE0141/secd_ram_controller.vhd (revision 105) @@ -0,0 +1,408 @@ +-- secd_ram_controller.vhd +-- +-- Multiplex the external 16 bit SRAM to the 32 bit interface required +-- by the CPU and provide for an 8 bit backside port for the 6809 to +-- read and write SECD memory + +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity secd_ram_controller is + port( + clk : in std_logic; + reset : in std_logic; + + secd_stopped : in std_logic; + + -- Internal interface to SECD (16k x 32) + din32 : in std_logic_vector(31 downto 0); + dout32 : out std_logic_vector(31 downto 0); + addr32 : in std_logic_vector(13 downto 0); + read32_enable : in std_logic; + write32_enable : in std_logic; + busy32 : out std_logic; + + -- Internal interface to 6809 (64k x 8) + clk8 : in std_logic; + din8 : in std_logic_vector(7 downto 0); + dout8 : out std_logic_vector(7 downto 0); + addr8 : in std_logic_vector(15 downto 0); + rw8 : in std_logic; + cs8_ram : in std_logic; + hold8 : out std_logic; + cs8_cf : in std_logic; + + -- External interface + ram_oen : out std_logic; + ram_cen : out std_logic; + ram_wen : out std_logic; + ram_io : inout std_logic_vector(15 downto 0); + ram_a : out std_logic_vector(20 downto 1); + ram_bhen : out std_logic; + ram_blen : out std_logic + ); +end; + +architecture external_ram of secd_ram_controller is + + type hold_state_type is ( hold_release_state, hold_request_state ); + + signal cf_hold_state : hold_state_type; + + signal cf_release : std_logic; + signal cf_count : std_logic_vector(3 downto 0); + + type state_type is (idle, + read32_high, read32_high_deselect, read32_low, read32_low_deselect, + write32_high, write32_high_deselect, write32_low, write32_low_deselect, + read8_ram, write8_ram, read8_cf, write8_cf ); + + signal state, next_state : state_type; + + signal read32_buff : std_logic_vector(31 downto 0); + signal read32_hen, read32_len : std_logic; + +begin + + +secd_ram_process : process( state, + read32_enable, write32_enable, addr32, din32, + cs8_ram, rw8, addr8, din8 ) +begin + case state is + when idle => + ram_a(20 downto 1) <= (others => '0'); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + dout8 <= (others => '0'); + if read32_enable = '1' then + hold8 <= '0'; + busy32 <= '1'; + next_state <= read32_high; + elsif write32_enable = '1' then + hold8 <= '0'; + busy32 <= '1'; + next_state <= write32_high; + elsif (cs8_ram = '1') and (rw8 = '1') then + hold8 <= '1'; + busy32 <= '1'; + next_state <= read8_ram; + elsif (cs8_ram = '1') and (rw8 = '0') then + hold8 <= '1'; + busy32 <= '1'; + next_state <= write8_ram; + elsif (cs8_cf = '1') and (rw8 = '1') then + hold8 <= '1'; + busy32 <= '1'; + next_state <= read8_cf; + elsif (cs8_cf = '1') and (rw8 = '0') then + hold8 <= '1'; + busy32 <= '1'; + next_state <= write8_cf; + else + hold8 <= '0'; + busy32 <= '0'; + next_state <= idle; + end if; + + when read32_high => + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= (others => 'Z'); + read32_hen <= '1'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= read32_high_deselect; + + when read32_high_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= read32_low; + + when read32_low => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '1'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= read32_low_deselect; + + when read32_low_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '0'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= idle; + + when write32_high => + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '1'; + ram_wen <= '0'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= din32(31 downto 16); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= write32_high_deselect; + + when write32_high_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= write32_low; + + when write32_low => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= din32(15 downto 0); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '0'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= write32_low_deselect; + + when write32_low_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '0'; + dout8 <= (others => '0'); + hold8 <= cs8_ram; + next_state <= idle; + + when read8_ram => + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= addr8(0); + ram_blen <= not addr8(0); + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + if addr8(0) = '0' then + dout8 <= ram_io(15 downto 8); + else + dout8 <= ram_io(7 downto 0); + end if; + hold8 <= '0'; + -- Synchronize on the CPU clock + if clk8 = '1' then + next_state <= idle; + else + next_state <= read8_ram; + end if; + + when write8_ram => + ram_a(1) <= '1'; + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= addr8(0); + ram_blen <= not addr8(0); + if addr8(0) = '0' then + ram_io(15 downto 8) <= din8; + ram_io( 7 downto 0) <= (others => 'Z'); + else + ram_io(15 downto 8) <= (others => 'Z'); + ram_io( 7 downto 0) <= din8; + end if; + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + hold8 <= '0'; + -- Synchronize on the CPU clock + if clk8 = '1' then + next_state <= idle; + else + next_state <= write8_ram; + end if; + + + when read8_cf => + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= ram_io(7 downto 0); + if cf_release = '1' then + hold8 <= '0'; + next_state <= idle; + else + hold8 <= '1'; + next_state <= read8_cf; + end if; + + when write8_cf => + ram_a(1) <= '1'; + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io(15 downto 8) <= (others => '0'); + ram_io( 7 downto 0) <= din8; + read32_hen <= '0'; + read32_len <= '0'; + busy32 <= '1'; + dout8 <= (others => '0'); + if cf_release = '1' then + hold8 <= '0'; + next_state <= idle; + else + hold8 <= '1'; + next_state <= write8_cf; + end if; + + when others => + null; + + end case; +end process; + + -- + -- RAM state machine + -- clock state transitions + -- and register 32 bit reads. + -- + -- Try experimenting with the clock edge + -- The Clock edge should be the same + -- as the transition edge of the + -- 12.5 MHz 6809 clock. + -- + ram_state_machine : process( clk, reset, read32_buff ) + begin + if reset = '1' then + state <= idle; + read32_buff <= (others => '0'); + elsif falling_edge( clk ) then + state <= next_state; + if read32_hen = '1' then + read32_buff(31 downto 16) <= ram_io; + end if; + if read32_len = '1' then + read32_buff(15 downto 0) <= ram_io; + end if; + end if; + dout32 <= read32_buff; + end process; + +-- +-- Hold CF access for a few cycles +-- synchronize with the CPU clock +-- hold release is set on the rising edge +-- of the CPU clock so that you have one +-- VGA clock cycle to return to the idle state +-- of the secd_ram_process state machine. +-- +cf_hold_proc: process( clk8, reset ) +begin + if reset = '1' then + cf_release <= '0'; + cf_count <= "0000"; + cf_hold_state <= hold_release_state; + elsif rising_edge( clk8 ) then + case cf_hold_state is + when hold_release_state => + cf_release <= '0'; + if cs8_cf = '1' then + cf_count <= "0011"; + cf_hold_state <= hold_request_state; + end if; + + when hold_request_state => + cf_count <= cf_count - "0001"; + if cf_count = "0000" then + cf_release <= '1'; + cf_hold_state <= hold_release_state; + end if; + when others => + null; + end case; + end if; + +end process; + +end; Index: System09_Trenz_TE0141/ram_controller.vhd =================================================================== --- System09_Trenz_TE0141/ram_controller.vhd (nonexistent) +++ System09_Trenz_TE0141/ram_controller.vhd (revision 105) @@ -0,0 +1,75 @@ +-- +-- ram_controller.vhd +-- + +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity ram_controller is + port( + reset : in std_logic; + clk : in std_logic; + cs_ram : in std_logic; + rw : in std_logic; + din : in std_logic_vector(7 downto 0); + dout : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(19 downto 0); + + -- External interface + ram_oen : out std_logic; + ram_cen : out std_logic; + ram_wen : out std_logic; + ram_io : inout std_logic_vector(15 downto 0); + ram_a : out std_logic_vector(20 downto 1); + ram_bhen : out std_logic; + ram_blen : out std_logic + ); +end; + +architecture external_ram of ram_controller is + +signal we : std_logic; + +begin + +-- +-- 1M byte SRAM Control +-- Processes to read and write memory based on bus signals +-- Uses bhe/ble controlled write +-- so that clock stretching can be performed on the CF +-- +ram_process: process( clk, addr, rw, + cs_ram, ram_io, din ) +begin + ram_wen <= rw; + ram_oen <= not rw; + ram_cen <= not cs_ram; + ram_bhen <= not( (not addr(0)) and clk ); + ram_blen <= not( addr(0) and clk ); + + ram_a(20) <= '0'; + ram_a(19 downto 1) <= addr(19 downto 1); + + if (rw = '0') and (addr(0) = '0') then + ram_io(15 downto 8) <= din; + else + ram_io(15 downto 8) <= "ZZZZZZZZ"; + end if; + + if (rw = '0') and (addr(0) = '1') then + ram_io(7 downto 0) <= din; + else + ram_io(7 downto 0) <= "ZZZZZZZZ"; + end if; + + if addr(0) = '0' then + dout <= ram_io(15 downto 8); + else + dout <= ram_io(7 downto 0); + end if; +end process; + +end; Index: System09_Trenz_TE0141/fep_toplevel.vhd =================================================================== --- System09_Trenz_TE0141/fep_toplevel.vhd (nonexistent) +++ System09_Trenz_TE0141/fep_toplevel.vhd (revision 105) @@ -0,0 +1,980 @@ +-- SECD Front End Processor derived from System09 written by John E. Kent +-- This core adheres to the GNU public license + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; +--use config.all; + +entity secd_fep_trenz is + port( + utmi_clkout : in Std_Logic; -- UTMI Clock input + utmi_databus16_8 : out Std_Logic; -- UTMI configuration input + + reset_sw : in Std_logic; -- Master Reset input (active low) + + -- PS/2 Keyboard + ps2_clk1 : inout Std_logic; + ps2_data1 : inout Std_Logic; + + -- Uart Interface + fpga_rxd : in Std_Logic; + fpga_txd : out Std_Logic; + fpga_cts : in Std_Logic; + fpga_rts : out Std_Logic; + + -- CRTC output signals + vsync_b : out Std_Logic; + hsync_b : out Std_Logic; + fpga_b : out Std_Logic_Vector(2 downto 0); + fpga_g : out Std_Logic_Vector(2 downto 0); + fpga_r : out Std_Logic_Vector(2 downto 0); + + -- LEDS & Switches + mm_led : out Std_Logic; + led : out Std_Logic_Vector(3 downto 0); + + joy_down : in Std_Logic; + joy_fire : in Std_Logic; + joy_left : in Std_Logic; + joy_right : in Std_Logic; + joy_up : in Std_Logic; + + -- LCD Display + lcd_e : out Std_Logic; + lcd_rw : out Std_Logic; + lcd_rs : out Std_Logic; + lcd_d : out Std_Logic_Vector(3 downto 0); + + -- Audio + aud_out : out std_logic_vector(4 downto 1); + + -- Memory interface + ram_a : out std_logic_vector(20 downto 1); + ram_io : inout std_logic_vector(15 downto 0); + ram_bhen : out std_logic; + ram_blen : out std_logic; + ram_cen : out std_logic; + ram_oen : out std_logic; + ram_wen : out std_logic; + + -- Compact flash + cf_reset : out std_logic; +-- cf_irq : in std_logic; + cf_iord : out std_logic; + cf_iowr : out std_logic; +-- cf_wait : in std_logic; +-- cf_dasp : in std_logic; +-- cf_pdiag : in std_logic; +-- cf_cd1 : in std_logic; +-- cf_cd2 : in std_logic; +-- iois16 : in std_logic; +-- cf_oe : out std_logic; + cf_pwr_en : out std_logic; + cf_cs0 : out std_logic; + cf_cs1 : out std_logic +-- cf_we : out std_logic; +-- cf_rew : out std_logic + ); +end secd_fep_trenz; + +------------------------------------------------------------------------------- +-- Architecture for System09 +------------------------------------------------------------------------------- +architecture rtl of secd_fep_trenz is + ----------------------------------------------------------------------------- + -- constants + ----------------------------------------------------------------------------- + constant fep_only : integer := 1; + + constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock + constant VGA_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock + constant CPU_Clock_Frequency : integer := 12500000; -- CPU Clock + constant BAUD_Rate : integer := 57600; -- Baud Rate + constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16; + + ----------------------------------------------------------------------------- + -- ChipScope Pro components and signals + ----------------------------------------------------------------------------- + +-- component icon +-- port(control0 : out std_logic_vector(35 downto 0)); +-- end component; + +-- component ila +-- port(control : in std_logic_vector(35 downto 0); +-- clk : in std_logic; +-- trig0 : in std_logic_vector(39 downto 0)); +-- end component; + +-- signal chipscope_control : std_logic_vector(35 downto 0); +-- signal ila_clock : std_logic; + + ----------------------------------------------------------------------------- + -- Signals + ----------------------------------------------------------------------------- + + -- Clocks + attribute buffer_type : string; + attribute period : string; + + signal vdu_clk : std_logic; -- 25 Mhz + attribute period of vdu_clk : signal is "40 ns"; + attribute buffer_type of vdu_clk : signal is "BUFG"; + + signal cpu_clk : std_logic; -- 12.5 Mhz + attribute buffer_type of cpu_clk : signal is "BUFG"; + + -- BOOT ROM + signal rom_cs : Std_logic; + signal rom_data_out : Std_Logic_Vector(7 downto 0); + + -- RAM + signal user_ram0_cs : std_logic; + signal user_ram0_dout : std_logic_vector(7 downto 0); + signal user_ram1_cs : std_logic; + signal user_ram1_dout : std_logic_vector(7 downto 0); + + -- UART Interface signals + signal uart_data_out : Std_Logic_Vector(7 downto 0); + signal uart_cs : Std_Logic; + signal uart_irq : Std_Logic; + signal baudclk : Std_Logic; + signal DCD_n : Std_Logic; + signal RTS_n : Std_Logic; + signal CTS_n : Std_Logic; + + -- keyboard port + signal keyboard_data_out : std_logic_vector(7 downto 0); + signal keyboard_cs : std_logic; + signal keyboard_irq : std_logic; + + -- CPU Interface signals + signal cpu_rw : std_logic; + signal cpu_vma : std_logic; + signal cpu_halt : std_logic; + signal cpu_hold : std_logic; + signal cpu_firq : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + + -- Compact Flash port + signal cf_data_out : std_logic_vector(7 downto 0); + signal cf_cs : std_logic; + signal cf_rd : std_logic; + signal cf_wr : std_logic; + + -- Video Display Unit + signal vdu_cs : std_logic; + signal vdu_data_out : std_logic_vector(7 downto 0); + + -- VGA output signals (distributed to VGA DAC) + signal red : std_logic; + signal green : std_logic; + signal blue : std_logic; + + -- System Reset (generated by key press) + signal reset : std_logic; + + -- LCD register select + signal lcd_cs : std_logic; + + -- LED register select + signal led_cs : std_logic; + signal led_reg : std_logic_vector(7 downto 0) := (others => '0'); + + -- Joystick buffer + signal joystick : std_logic_vector(7 downto 0); + + -- LED Flasher + signal blink_count : std_logic_vector(25 downto 0) := (others => '0'); + + -- SECD interface + signal secd_button : std_logic := '0'; + signal secd_stop : std_logic := '1'; + signal secd_stopped : std_logic := '1'; + signal secd_state : std_logic_vector(1 downto 0); + signal secd_ram_addr_hi : std_logic_vector(7 downto 0) := (others => '0'); + signal secd_ram_addr_high_cs : std_logic := '0'; + signal secd_ram_cs : std_logic := '0'; + signal secd_control_cs : std_logic := '0'; + + -- SECD RAM Controller interface + signal secd_ram_busy : std_logic; + + -- RAM signal taps + signal ram_bhenx : std_logic; + signal ram_blenx : std_logic; + signal ram_cenx : std_logic; + signal ram_oenx : std_logic; + signal ram_wenx : std_logic; + + -- Interface signals for SECD + signal secd_ram_din32 : std_logic_vector(31 downto 0); + signal secd_ram_dout32 : std_logic_vector(31 downto 0); + signal secd_ram_addr32 : std_logic_vector(13 downto 0); + signal secd_ram_read32 : std_logic; + signal secd_ram_write32 : std_logic; + + -- Interface signals for 6809 + signal secd_ram_dout8 : std_logic_vector(7 downto 0); + signal secd_ram_hold : std_logic; + + -- Locked signal of clock synthesizer + signal clock_locked : std_logic; + signal ila_clock :std_logic; +----------------------------------------------------------------- +-- +-- CPU09 CPU core +-- +----------------------------------------------------------------- + +component cpu09 + port ( + clk : in std_logic; + rst : in std_logic; + rw : out std_logic; -- Asynchronous memory interface + vma : out std_logic; + address : out std_logic_vector(15 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + halt : in std_logic; + hold : in std_logic; + irq : in std_logic; + nmi : in std_logic; + firq : in std_logic + ); +end component; + + +---------------------------------------- +-- +-- 16KByte Block RAM Mais Forth ROM +-- +---------------------------------------- +component maisforth_rom_16k + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (13 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); +end component; + +---------------------------------------- +-- +-- 8KBytes Block RAM for FLEX9 +-- $C000 - $DFFF +-- +---------------------------------------- +component ram_2k + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (12 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); +end component; + +----------------------------------------------------------------- +-- +-- Open Cores Mini UART +-- +----------------------------------------------------------------- + +component ACIA_6850 + port ( + clk : in Std_Logic; -- System Clock + rst : in Std_Logic; -- Reset input (active high) + cs : in Std_Logic; -- miniUART Chip Select + rw : in Std_Logic; -- Read / Not Write + irq : out Std_Logic; -- Interrupt + Addr : in Std_Logic; -- Register Select + DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In + DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out + RxC : in Std_Logic; -- Receive Baud Clock + TxC : in Std_Logic; -- Transmit Baud Clock + RxD : in Std_Logic; -- Receive Data + TxD : out Std_Logic; -- Transmit Data + DCD_n : in Std_Logic; -- Data Carrier Detect + CTS_n : in Std_Logic; -- Clear To Send + RTS_n : out Std_Logic -- Request To send + ); +end component; + +----------------------------------------------------------------- +-- +-- ACIA Clock divider +-- +----------------------------------------------------------------- + +component ACIA_Clock + generic ( + SYS_Clock_Frequency : integer := VGA_Clock_Frequency; + ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency + ); + port ( + clk : in Std_Logic; -- System Clock Input + ACIA_clk : out Std_logic -- ACIA Clock output + ); +end component; + + +---------------------------------------- +-- +-- PS/2 Keyboard +-- +---------------------------------------- + +component keyboard + generic( + KBD_Clock_Frequency : integer := CPU_Clock_Frequency + ); + port( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic + ); +end component; + +---------------------------------------- +-- +-- Video Display Unit. +-- +---------------------------------------- +component vdu8 + generic( + VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ + VGA_CLOCK_FREQUENCY : integer := VGA_Clock_Frequency; -- HZ + VGA_HOR_CHARS : integer := 80; -- CHARACTERS + VGA_VER_CHARS : integer := 25; -- CHARACTERS + VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS + VGA_LINES_PER_CHAR : integer := 16; -- LINES + VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS + VGA_HOR_SYNC : integer := 96; -- PIXELS + VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS + VGA_VER_BACK_PORCH : integer := 13; -- LINES + VGA_VER_SYNC : integer := 1; -- LINES + VGA_VER_FRONT_PORCH : integer := 36 -- LINES + ); + port( + -- control register interface + vdu_clk : in std_logic; -- CPU Clock - 12.5MHz + vdu_rst : in std_logic; + vdu_cs : in std_logic; + vdu_rw : in std_logic; + vdu_addr : in std_logic_vector(2 downto 0); + vdu_data_in : in std_logic_vector(7 downto 0); + vdu_data_out : out std_logic_vector(7 downto 0); + + -- vga port connections + vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz + vga_red_o : out std_logic; + vga_green_o : out std_logic; + vga_blue_o : out std_logic; + vga_hsync_o : out std_logic; + vga_vsync_o : out std_logic + ); +end component; + +begin + + ----------------------------------------------------------------- + -- + -- ChipsScope Pro cores + -- + ----------------------------------------------------------------- + +-- i_icon : icon +-- port map(control0 => chipscope_control); +-- +-- i_ila : ila +-- port map(control => chipscope_control, +-- clk => ila_clock, +-- trig0(15 downto 8) => cpu_data_in, +-- trig0(23 downto 16) => cpu_data_out, +-- trig0(39 downto 24) => cpu_addr, +-- trig0(0) => cpu_clk, +-- trig0(1) => cpu_vma, +-- trig0(2) => ram_bhenx, +-- trig0(3) => ram_blenx, +-- trig0(4) => ram_cenx, +-- trig0(5) => ram_oenx, +-- trig0(6) => ram_wenx, +-- trig0(7) => vdu_clk); + + ----------------------------------------------------------------- + -- + -- CPU09 CPU core + -- + ----------------------------------------------------------------- + + my_cpu : entity cpu09 port map ( + clk => cpu_clk, + rst => reset, + rw => cpu_rw, + vma => cpu_vma, + address => cpu_addr, + data_in => cpu_data_in, + data_out => cpu_data_out, + halt => cpu_halt, + hold => cpu_hold, + irq => cpu_irq, + nmi => cpu_nmi, + firq => cpu_firq + ); + + ---------------------------------------- + -- + -- Maisforth ROM (Xilinx Block RAM, 16k) + -- + ---------------------------------------- + + my_maisforth_rom_16k : entity maisforth_rom_16k port map ( + clk => cpu_clk, + rst => reset, + cs => rom_cs, + rw => '1', + addr => cpu_addr(13 downto 0), + rdata => rom_data_out, + wdata => cpu_data_out + ); + + ----------------------------------------------------------------------------- + -- + -- Internal RAM (Xilinx Block RAM, 4k) + -- + ----------------------------------------------------------------------------- + + my_user_ram0_2k : entity ram_2k port map ( + clk => cpu_clk, + rst => reset, + cs => user_ram0_cs, + rw => cpu_rw, + addr => cpu_addr(10 downto 0), + rdata => user_ram0_dout, + wdata => cpu_data_out + ); + + my_user_ram1_2k : entity ram_2k port map ( + clk => cpu_clk, + rst => reset, + cs => user_ram1_cs, + rw => cpu_rw, + addr => cpu_addr(10 downto 0), + rdata => user_ram1_dout, + wdata => cpu_data_out + ); + + ----------------------------------------------------------------- + -- + -- 6850 ACIA + -- + ----------------------------------------------------------------- + + my_uart : entity acia_6850 port map ( + clk => cpu_clk, + rst => reset, + cs => uart_cs, + rw => cpu_rw, + irq => uart_irq, + Addr => cpu_addr(0), + Datain => cpu_data_out, + DataOut => uart_data_out, + RxC => baudclk, + TxC => baudclk, + RxD => fpga_rxd, + TxD => fpga_txd, + DCD_n => dcd_n, + CTS_n => fpga_cts, + RTS_n => fpga_rts + ); + + +---------------------------------------- +-- +-- PS/2 Keyboard Interface +-- +---------------------------------------- +my_keyboard : keyboard + generic map ( + KBD_Clock_Frequency => CPU_Clock_frequency + ) + port map( + clk => cpu_clk, + rst => reset, + cs => keyboard_cs, + rw => cpu_rw, + addr => cpu_addr(0), + data_in => cpu_data_out(7 downto 0), + data_out => keyboard_data_out(7 downto 0), + irq => keyboard_irq, + kbd_clk => ps2_clk1, + kbd_data => ps2_data1 + ); + +---------------------------------------- +-- +-- Video Display Unit instantiation +-- +---------------------------------------- +my_vdu : vdu8 + generic map( + VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ + VGA_CLOCK_FREQUENCY => VGA_Clock_Frequency, -- HZ + VGA_HOR_CHARS => 80, -- CHARACTERS + VGA_VER_CHARS => 25, -- CHARACTERS + VGA_PIXELS_PER_CHAR => 8, -- PIXELS + VGA_LINES_PER_CHAR => 16, -- LINES + VGA_HOR_BACK_PORCH => 40, -- PIXELS + VGA_HOR_SYNC => 96, -- PIXELS + VGA_HOR_FRONT_PORCH => 24, -- PIXELS + VGA_VER_BACK_PORCH => 13, -- LINES + VGA_VER_SYNC => 1, -- LINES + VGA_VER_FRONT_PORCH => 36 -- LINES + ) + port map( + + -- Control Registers + vdu_clk => cpu_clk, -- 12.5 MHz System Clock in + vdu_rst => reset, + vdu_cs => vdu_cs, + vdu_rw => cpu_rw, + vdu_addr => cpu_addr(2 downto 0), + vdu_data_in => cpu_data_out, + vdu_data_out => vdu_data_out, + + -- vga port connections + vga_clk => vdu_clk, -- 25 MHz VDU pixel clock + vga_red_o => red, + vga_green_o => green, + vga_blue_o => blue, + vga_hsync_o => hsync_b, + vga_vsync_o => vsync_b + ); + + ---------------------------------------- + -- + -- Clock Synthesis instantiation + -- + ---------------------------------------- + + my_clock_synthesis : entity clock_synthesis port map ( + clk_30mhz => utmi_clkout, + vdu_clk => vdu_clk, + cpu_clk => cpu_clk, + locked => clock_locked ); +-- clk_60mhz => ila_clock); + +--make_secd: if fep_only /= '1' generate +-- ---------------------------------------- +-- -- +-- -- SECD CPU instantiation +-- -- +-- ---------------------------------------- +-- +-- my_secd_system : entity secd_system port map ( +-- clk => cpu_clk, +-- reset => reset, +-- button => secd_button, +-- ram_read => secd_ram_read32, +-- ram_in => secd_ram_dout32, +-- ram_write => secd_ram_write32, +-- ram_out => secd_ram_din32, +-- ram_a => secd_ram_addr32, +-- ram_busy => secd_ram_busy, +-- stop_input => secd_stop, +-- stopped => secd_stopped, +-- state => secd_state +-- ); +--end generate; + + ---------------------------------------- + -- + -- SECD RAM Controller instantiation + -- + ---------------------------------------- + + my_secd_ram : entity secd_ram_controller port map ( + clk => vdu_clk, + reset => reset, + secd_stopped => secd_stopped, + + -- SECD interface + din32 => secd_ram_din32, + dout32 => secd_ram_dout32, + addr32 => secd_ram_addr32, + read32_enable => secd_ram_read32, + write32_enable => secd_ram_write32, + busy32 => secd_ram_busy, + + -- 6809 interface + clk8 => cpu_clk, + din8 => cpu_data_out, + dout8 => secd_ram_dout8, + addr8(15 downto 8) => secd_ram_addr_hi, + addr8(7 downto 0) => cpu_addr(7 downto 0), + cs8_ram => secd_ram_cs, + rw8 => cpu_rw, + hold8 => secd_ram_hold, + + -- Compact Flash interface + cs8_cf => cf_cs, + + -- external interface + ram_oen => ram_oenx, + ram_cen => ram_cenx, + ram_wen => ram_wenx, + ram_io => ram_io, + ram_a => ram_a, + ram_bhen => ram_bhenx, + ram_blen => ram_blenx + ); + + +---------------------------------------- +-- +-- ACIA Clock +-- +---------------------------------------- +my_ACIA_Clock : ACIA_Clock + generic map( + SYS_Clock_Frequency => VGA_Clock_Frequency, + ACIA_Clock_Frequency => ACIA_Clock_Frequency + ) + port map( + clk => vdu_clk, + acia_clk => baudclk + ); + + ---------------------------------------------------------------------- + -- + -- Process to decode memory map + -- + ---------------------------------------------------------------------- + + mem_decode : process( cpu_addr, cpu_rw, cpu_vma, + rom_data_out, + user_ram0_dout, + user_ram1_dout, + uart_data_out, + keyboard_data_out, + joystick, + vdu_data_out, + cf_data_out, + cpu_data_out, + secd_state, secd_stopped, secd_ram_dout8, secd_ram_addr_hi ) + + begin + user_ram0_cs <= '0'; + user_ram1_cs <= '0'; + rom_cs <= '0'; + uart_cs <= '0'; + keyboard_cs <= '0'; + vdu_cs <= '0'; + cf_cs <= '0'; + lcd_cs <= '0'; + led_cs <= '0'; + cpu_data_in <= X"00"; + + secd_control_cs <= '0'; + secd_ram_cs <= '0'; + secd_ram_addr_high_cs <= '0'; + + case cpu_addr(15 downto 14) is + + -- Maisforth ROM - $C000 - $FFFF + when "11" => + cpu_data_in <= rom_data_out; + rom_cs <= cpu_vma; -- read ROM + + -- RAM - $0000-$3FFF + when "00" => + case cpu_addr(13 downto 11) is + when "000" => + cpu_data_in <= user_ram0_dout; + user_ram0_cs <= cpu_vma; + + when "001" => + cpu_data_in <= user_ram1_dout; + user_ram1_cs <= cpu_vma; + + when others => + cpu_data_in <= (others => '0'); + + end case; + + -- Unmapped - $4000-$7FFF, read as FF + when "01" => + cpu_data_in <= X"FF"; + + -- I/O - $8000-$BFFF - Do additional decoding + when "10" => + case cpu_addr(13 downto 8) is + + -- Real I/O $B000 - $B0FF + when "110000" => + case cpu_addr(7 downto 4) is + + -- UART / ACIA $B000 + when X"0" => + cpu_data_in <= uart_data_out; + uart_cs <= cpu_vma; + + -- Keyboard port $B010 - $B01F + -- Note in latest System09 + -- I have moved the Keyboard + -- to $E020 to make way for the + -- Floppy Disk Controller at $E01X + -- JK. 10th Aug 07 + when X"1" => + cpu_data_in <= keyboard_data_out; + keyboard_cs <= cpu_vma; + + -- VDU port $B020 - $B02F + -- Note in latest System09 + -- I have moved the VDU to + -- $E030 - JK. 10th Aug 07 + when X"2" => + cpu_data_in <= vdu_data_out; + vdu_cs <= cpu_vma; + + -- CF port $B040 - $B04F + -- Note in latest System09 + -- I have moved the CF to + -- $E040 - JK. 10th Aug 07 + when X"4" => + cpu_data_in <= secd_ram_dout8; + cf_cs <= cpu_vma; + + -- Joystick $B0D0 (read only) + when X"D" => + if cpu_addr(3 downto 0) = "0000" then + cpu_data_in <= joystick; + end if; + + -- LED $B0E0 (write only) + when X"E" => + if cpu_addr(3 downto 0) = "0000" then + led_cs <= cpu_vma; + end if; + + -- LCD Display $B0F0 (write only) + when X"F" => + if cpu_addr(3 downto 0) = "0000" then + lcd_cs <= cpu_vma; + end if; + + when others => + null; + end case; + + -- SECD Control registers - $B100 + when "110001" => + + case cpu_addr(7 downto 0) is + + -- $B140 -> SECD Status + when X"40" => + secd_control_cs <= cpu_vma; + cpu_data_in(0) <= secd_stopped; + cpu_data_in(2 downto 1) <= secd_state; + + -- $B141 -> SECD Address High + when X"41" => + secd_ram_addr_high_cs <= cpu_vma; + cpu_data_in <= secd_ram_addr_hi; + + when others => + null; + + end case; + + -- SECD mapped memory page - $B200 + when "110010" => + cpu_data_in <= secd_ram_dout8; + secd_ram_cs <= cpu_vma; + + when others => + null; + + end case; + + when others => + null; + + end case; + end process; + +-- +-- Compact Flash Control +-- +compact_flash: process( reset_sw, + cpu_addr, cpu_rw, cpu_vma, cpu_data_out, + cf_cs, cf_rd, cf_wr ) +begin + cf_reset <= reset_sw; + cf_cs0 <= not( cf_cs ) or cpu_addr(3); + cf_cs1 <= not( cf_cs and cpu_addr(3)); + cf_wr <= cf_cs and (not cpu_rw); + cf_rd <= cf_cs and cpu_rw; + cf_iowr <= not cf_wr; + cf_iord <= not cf_rd; + cf_pwr_en <= '0'; +end process; + + +-- +-- Interrupts and other bus control signals +-- + interrupts : process( reset_sw, uart_irq, keyboard_irq, reset, joy_up, secd_ram_hold, secd_ram_cs ) + begin + cpu_irq <= keyboard_irq; + cpu_nmi <= not joy_up; + cpu_firq <= uart_irq; + cpu_halt <= '0'; + cpu_hold <= secd_ram_hold; + end process; + + -- + -- LCD write register + -- + lcd_control : process(lcd_cs, cpu_clk, cpu_data_out) + begin + if falling_edge(cpu_clk) then + if lcd_cs = '1' and cpu_rw = '0' then + lcd_d <= cpu_data_out(3 downto 0); + lcd_e <= cpu_data_out(4); + lcd_rw <= cpu_data_out(5); + lcd_rs <= cpu_data_out(6); + end if; + end if; + end process; + + -- + -- LED write register + -- + led_control : process(led_reg, led_cs, cpu_clk, cpu_data_out) + begin + if falling_edge(cpu_clk) then + if led_cs = '1' and cpu_rw = '0' then + led_reg(3 downto 0) <= cpu_data_out(3 downto 0); + else + led_reg <= led_reg; + end if; + end if; + + led <= led_reg(3 downto 0); + end process; + + -- SECD control register + -- + secd_control : process(secd_control_cs, cpu_clk, cpu_data_out) + begin + if falling_edge(cpu_clk) then + if secd_control_cs = '1' and cpu_rw = '0' then + secd_stop <= cpu_data_out(0); + secd_button <= cpu_data_out(1); + end if; + end if; + end process; + + -- + -- SECD RAM Adressing + -- + + secd_ram_addressing_high : process(cpu_clk, cpu_rw, cpu_data_out, secd_ram_addr_high_cs) + begin + if falling_edge(cpu_clk) then + if cpu_rw = '0' and secd_ram_addr_high_cs = '1' then + secd_ram_addr_hi <= cpu_data_out; + end if; + end if; + end process; + + -- + -- Joystick register + -- + read_joystick : process(cpu_clk, joy_up, joy_right, joy_down, joy_left, joy_fire) + begin + if rising_edge(cpu_clk) then + joystick(0) <= joy_up; + joystick(1) <= joy_right; + joystick(2) <= joy_down; + joystick(3) <= joy_left; + joystick(4) <= joy_fire; + joystick(7 downto 5) <= (others => '0'); + end if; + end process; + +-- +-- LED Flasher +-- + my_led_flasher: process(vdu_clk, reset, blink_count) + begin + if reset = '1' then + blink_count <= (others => '0'); + elsif rising_edge(vdu_clk) then + blink_count <= blink_count + 1; + end if; + + mm_led <= blink_count(25); + + end process; + +-- Set UART DCD to always true + DCD_n <= '0'; + +-- +-- Feed RGB DAC +-- + fpga_r(0) <= red; + fpga_r(1) <= red; + fpga_r(2) <= red; + fpga_g(0) <= green; + fpga_g(1) <= green; + fpga_g(2) <= green; + fpga_b(0) <= blue; + fpga_b(1) <= blue; + fpga_b(2) <= blue; + + -- set USB PHY to 16 bit mode so that it generates a 30 Mhz Clock + utmi_databus16_8 <= '1'; + + -- Hold system in reset until the clock is locked or when the reset + -- key is pressed. + reset <= not reset_sw or not clock_locked; + + aud_out <= (others => '0'); + + ram_bhen <= ram_bhenx; + ram_blen <= ram_blenx; + ram_cen <= ram_cenx; + ram_oen <= ram_oenx; + ram_wen <= ram_wenx; + + secd_ram_din32 <= (others => '0'); + secd_ram_addr32 <= (others => '0'); + secd_ram_read32 <= '0'; + secd_ram_write32 <= '0'; + +end; + Index: System09_Trenz_TE0141/maisforth_rom.aux =================================================================== --- System09_Trenz_TE0141/maisforth_rom.aux (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom.aux (revision 105) @@ -0,0 +1,13 @@ +t b +l an601.bin +t h +s maisforth_rom0.vhd 0000 07ff +s maisforth_rom1.vhd 0800 0fff +s maisforth_rom2.vhd 1000 17ff +s maisforth_rom3.vhd 1800 1fff +s maisforth_rom4.vhd 2000 27ff +s maisforth_rom5.vhd 2800 2fff +s maisforth_rom6.vhd 3000 37ff +s maisforth_rom7.vhd 3800 3fff +q + Index: System09_Trenz_TE0141/toplevel.ucf =================================================================== --- System09_Trenz_TE0141/toplevel.ucf (nonexistent) +++ System09_Trenz_TE0141/toplevel.ucf (revision 105) @@ -0,0 +1,173 @@ +#-------------------------------------------------------------------------------- +#-- Copyright (C) 2004 Trenz Electronic GmbH +#-- www.trenz-electronic.de +#-- Author: Kolja Sulimma +#-------------------------------------------------------------------------------- +#-- Project: TE-XC3S Application Note: Pong Demo +#-- File: toplevel.ucf +#-- Description: Pin assignments for the Pong Demo +#-- History: V1.0 2004-10-11 KS created +#-------------------------------------------------------------------------------- +#-- This program is free software; you can redistribute it and/or +#-- modify it under the terms of the GNU General Public License +#-- as published by the Free Software Foundation; either version 2 +#-- of the License, or (at your option) any later version. + +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. + +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +#Reset +NET "reset_sw" LOC = "R16" | PULLUP; + +#led on micromodule +NET "mm_led" LOC = "N6" ; + +#mandatory umti signals to get a clock +NET "utmi_clkout" LOC = "D9" ; +NET "utmi_databus16_8" LOC = "B14" ; + +#utmi signals only used with USB function +NET "utmi_opmode1" LOC = "C6" ; +NET "utmi_reset" LOC = "B4" ; +NET "utmi_termselect" LOC = "B6" ; +NET "utmi_txvalid" LOC = "B12" ; +NET "utmi_xcvrselect" LOC = "D6" ; + +#vga output +NET "fpga_b<0>" LOC = "M16" | DRIVE = 24 ; +NET "fpga_b<1>" LOC = "M15" | DRIVE = 24 ; +NET "fpga_b<2>" LOC = "M14" | DRIVE = 24 ; +NET "fpga_g<0>" LOC = "N16" | DRIVE = 24 ; +NET "fpga_g<1>" LOC = "M13" | DRIVE = 24 ; +NET "fpga_g<2>" LOC = "L13" | DRIVE = 24 ; +NET "fpga_r<0>" LOC = "P16" | DRIVE = 24 ; +NET "fpga_r<1>" LOC = "N14" | DRIVE = 24 ; +NET "fpga_r<2>" LOC = "N15" | DRIVE = 24 ; +NET "hsync_b" LOC = "J13" ; +NET "vsync_b" LOC = "R1" ; + +#keyboard/mouse interfaces +NET "ps2_clk1" LOC = "C1" ; +#NET "ps2_clk2" LOC = "B1" ; +NET "ps2_data1" LOC = "C2" ; +#NET "ps2_data2" LOC = "C3" ; + +#joystick and buttons +NET "joy_down" LOC = "P15" ; +NET "joy_fire" LOC = "T14" ; +NET "joy_left" LOC = "K13" ; +NET "joy_right" LOC = "R13" ; +NET "joy_up" LOC = "P14" ; + +#leds on baseboard +NET "led<0>" LOC = "T13" ; +NET "led<1>" LOC = "R12" ; +NET "led<2>" LOC = "T12" ; +NET "led<3>" LOC = "R11" ; + +#audio +NET "aud_out<1>" LOC = "D10"; +NET "aud_out<2>" LOC = "E10"; +NET "aud_out<3>" LOC = "D11"; +NET "aud_out<4>" LOC = "D12"; + +#lcd +NET "lcd_d<3>" LOC = "M1"; +NET "lcd_d<2>" LOC = "L4"; +NET "lcd_d<1>" LOC = "L5"; +NET "lcd_d<0>" LOC = "N1"; +NET "lcd_e" LOC = "N2"; +NET "lcd_rw" LOC = "N3"; +NET "lcd_rs" LOC = "P1"; + +#rs232 +NET "fpga_cts" LOC = "K12" ; +NET "fpga_rts" LOC = "E11" ; +NET "fpga_rxd" LOC = "L12" ; +NET "fpga_txd" LOC = "J14" ; + +#ram, flash +NET "ram_a<0>" LOC = "D14" ; +NET "ram_a<1>" LOC = "K15" ; +NET "ram_a<2>" LOC = "M3" ; +NET "ram_a<3>" LOC = "L2" ; +NET "ram_a<4>" LOC = "L3" ; +NET "ram_a<5>" LOC = "K1" ; +NET "ram_a<6>" LOC = "K2" ; +NET "ram_a<7>" LOC = "J2" ; +NET "ram_a<8>" LOC = "J1" ; +NET "ram_a<9>" LOC = "G4" ; +NET "ram_a<10>" LOC = "F2" ; +NET "ram_a<11>" LOC = "F3" ; +NET "ram_a<12>" LOC = "E1" ; +NET "ram_a<13>" LOC = "E2" ; +NET "ram_a<14>" LOC = "E3" ; +NET "ram_a<15>" LOC = "D1" ; +NET "ram_a<16>" LOC = "D2" ; +NET "ram_a<17>" LOC = "B16" ; +NET "ram_a<18>" LOC = "H4" ; +NET "ram_a<19>" LOC = "H3"; +NET "ram_a<20>" LOC = "G3"; +NET "ram_io<0>" LOC = "H15" ; +NET "ram_io<1>" LOC = "H14" ; +NET "ram_io<2>" LOC = "G16" ; +NET "ram_io<3>" LOC = "G14" ; +NET "ram_io<4>" LOC = "F14" ; +NET "ram_io<5>" LOC = "E15" ; +NET "ram_io<6>" LOC = "D16" ; +NET "ram_io<7>" LOC = "E13" ; +NET "ram_io<8>" LOC = "H16" ; +NET "ram_io<9>" LOC = "H13" ; +NET "ram_io<10>" LOC = "G15" ; +NET "ram_io<11>" LOC = "F15" ; +NET "ram_io<12>" LOC = "E16" ; +NET "ram_io<13>" LOC = "E14" ; +NET "ram_io<14>" LOC = "D15" ; +NET "ram_io<15>" LOC = "C16" ; +NET "ram_bhen" LOC = "L14" ; +NET "ram_blen" LOC = "L15" ; +NET "ram_cen" LOC = "M2" ; +NET "ram_oen" LOC = "K16" ; +NET "ram_wen" LOC = "G1" ; + +#flash memory +NET "fl_resetn" LOC = "G2" ; +NET "fl_cen" LOC = "K14"; +NET "fl_oen" LOC = "J16"; +NET "fl_byten" LOC = "C15"; +NET "fl_busyn" LOC = "H1" ; + +#compact flash +NET "cf_we" LOC = "D8"; +NET "cf_reg" LOC = "G5"; +NET "cf_cs0" LOC = "D7"; +NET "cf_cs1" LOC = "D5"; +NET "cf_reset" LOC = "E6"; +NET "cf_irq" LOC = "E4" | PULLUP; +NET "cf_iord" LOC = "F4"; +NET "cf_iowr" LOC = "F5"; +NET "cf_wait" LOC = "E7" | PULLUP; +NET "cf_dasp" LOC = "J4" | PULLUP; +NET "cf_pdiag" LOC = "J3" | PULLUP; +NET "cf_cd1" LOC = "K5" | PULLUP; +NET "cf_cd2" LOC = "K4" | PULLUP; +NET "iois16" LOC = "K3" | PULLUP; +NET "cf_oe" LOC = "M4"; +NET "cf_pwr_en" LOC = "P2"; + +#ir_data +NET "ir_data" LOC = "D3" ; + + + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE Index: System09_Trenz_TE0141/secd_ram_controller_hans.vhd =================================================================== --- System09_Trenz_TE0141/secd_ram_controller_hans.vhd (nonexistent) +++ System09_Trenz_TE0141/secd_ram_controller_hans.vhd (revision 105) @@ -0,0 +1,379 @@ +-- secd_ram_controller.vhd +-- +-- Multiplex the external 16 bit SRAM to the 32 bit interface required +-- by the CPU and provide for an 8 bit backside port for the 6809 to +-- read and write SECD memory + +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity secd_ram_controller is + port( + clk : in std_logic; + reset : in std_logic; + + secd_stopped : in std_logic; + + -- Internal interface to SECD (16k x 32) + din32 : in std_logic_vector(31 downto 0); + dout32 : out std_logic_vector(31 downto 0); + addr32 : in std_logic_vector(13 downto 0); + read32_enable : in std_logic; + write32_enable : in std_logic; + busy32 : out std_logic; + + -- Internal interface to 6809 (64k x 8) + clk8 : in std_logic; + din8 : in std_logic_vector(7 downto 0); + dout8 : out std_logic_vector(7 downto 0); + addr8 : in std_logic_vector(15 downto 0); + rw8 : in std_logic; + cs8_ram : in std_logic; + hold8 : out std_logic; + cs8_cf : in std_logic; + + -- External interface + ram_oen : out std_logic; + ram_cen : out std_logic; + ram_wen : out std_logic; + ram_io : inout std_logic_vector(15 downto 0); + ram_a : out std_logic_vector(20 downto 1); + ram_bhen : out std_logic; + ram_blen : out std_logic + ); +end; + +architecture external_ram of secd_ram_controller is + + type hold_state_type is ( hold_release_state, hold_request_state ); + + signal cf_hold_state : hold_state_type; + + signal cf_release : std_logic; + signal cf_count : std_logic_vector(3 downto 0); + + type state_type is (idle, + read32_high, read32_high_deselect, read32_low, + write32_high, write32_high_deselect, write32_low, + read8_ram, write8_ram, read8_cf, write8_cf ); + + signal state : state_type; + signal dout8_en : std_logic; + +begin + + + secd_ram_process : process( clk, state, reset, + read32_enable, write32_enable, addr32, din32, + cs8_ram, rw8, addr8, din8 ) + begin + if reset = '1' then + ram_a(20 downto 1) <= (others => '0'); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + dout8_en <= '0'; + hold8 <= '0'; + busy32 <= '0'; + state <= idle; + elsif rising_edge(clk) then + case state is + when idle => + ram_a(20 downto 1) <= (others => '0'); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + dout8_en <= '0'; + if read32_enable = '1' then + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= '0'; + ram_blen <= '0'; + hold8 <= cs8_ram or cs8_cf; + busy32 <= '1'; + state <= read32_high; + elsif write32_enable = '1' then + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '1'; + ram_wen <= '0'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= din32(31 downto 16); + hold8 <= cs8_ram or cs8_cf; + busy32 <= '1'; + state <= write32_high; + elsif (cs8_ram = '1') and (rw8 = '1') then + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= addr8(0); + ram_blen <= not addr8(0); + dout8_en <= '1'; + hold8 <= '0'; + busy32 <= '1'; + state <= read8_ram; + elsif (cs8_ram = '1') and (rw8 = '0') then + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '0'; + ram_oen <= '1'; + ram_wen <= '0'; + ram_bhen <= addr8(0); + ram_blen <= not addr8(0); + if addr8(0) = '0' then + ram_io(15 downto 8) <= din8; + ram_io( 7 downto 0) <= (others => 'Z'); + else + ram_io(15 downto 8) <= (others => 'Z'); + ram_io( 7 downto 0) <= din8; + end if; + hold8 <= '0'; + busy32 <= '1'; + state <= write8_ram; + elsif (cs8_cf = '1') and (rw8 = '1') then + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + dout8_en <= '1'; + busy32 <= '1'; + if cf_release = '1' then + hold8 <= '0'; + state <= read8_cf; + else + hold8 <= '1'; + state <= idle; + end if; + elsif (cs8_cf = '1') and (rw8 = '0') then + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + busy32 <= '1'; + if addr8(0) = '0' then + ram_io(15 downto 8) <= din8; + ram_io( 7 downto 0) <= (others => 'Z'); + else + ram_io(15 downto 8) <= (others => 'Z'); + ram_io( 7 downto 0) <= din8; + end if; + if cf_release = '1' then + hold8 <= '0'; + state <= write8_cf; + else + hold8 <= '1'; + state <= idle; + end if; + else + hold8 <= '0'; + busy32 <= '0'; + state <= idle; + end if; + + when read32_high => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + dout32(31 downto 16) <= ram_io; + busy32 <= '1'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= read32_high_deselect; + + when read32_high_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '0'; + ram_wen <= '1'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= (others => 'Z'); + busy32 <= '1'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= read32_low; + + when read32_low => + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + dout32(15 downto 0) <= ram_io; + busy32 <= '0'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= idle; + + when write32_high => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + busy32 <= '1'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= write32_high_deselect; + + when write32_high_deselect => + ram_a(1) <= '1'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '0'; + ram_oen <= '1'; + ram_wen <= '0'; + ram_bhen <= '0'; + ram_blen <= '0'; + ram_io <= din32(15 downto 0); + busy32 <= '1'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= write32_low; + + when write32_low => + ram_a(1) <= '0'; + ram_a(20 downto 2) <= "00000" & addr32(13 downto 0); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + busy32 <= '0'; + dout8_en <= '0'; + hold8 <= cs8_ram or cs8_cf; + state <= idle; + + when read8_ram => + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_io <= (others => 'Z'); + busy32 <= '0'; + dout8_en <= '0'; + hold8 <= '0'; + state <= idle; + + when write8_ram => + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_io(15 downto 0) <= (others => 'Z'); + busy32 <= '0'; + dout8_en <= '0'; + hold8 <= '0'; + state <= idle; + + when read8_cf => + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + ram_io <= (others => 'Z'); + busy32 <= '0'; + dout8_en <= '0'; + hold8 <= '0'; + state <= idle; + + when write8_cf => + ram_a(1) <= '1'; + ram_a(20 downto 1) <= "00000" & addr8(15 downto 1); + ram_cen <= '1'; + ram_oen <= '1'; + ram_wen <= '1'; + ram_bhen <= '1'; + ram_blen <= '1'; + busy32 <= '1'; + dout8_en <= '0'; + hold8 <= '0'; + state <= idle; + + when others => + null; + + end case; + end if; + end process; + +-- +-- 8 Bit data bus output enable process +-- +-- The point of this process is that data must be +-- passed through from the ram input, +-- and not clocked, so it is ready for the CPU +-- on the trailing clock edge +-- +dout8_selector : process( dout8_en, addr8, ram_io ) +begin + if dout8_en = '0' then + dout8 <= ( others => '0' ); + else + if addr8(0) = '0' then + dout8 <= ram_io(15 downto 8); + else + dout8 <= ram_io(7 downto 0); + end if; + end if; +end process; + +-- +-- Hold CF access for a few cycles +-- synchronize with the CPU clock +-- hold release is set on the rising edge +-- of the CPU clock so that you have one +-- VGA clock cycle to return to the idle state +-- of the secd_ram_process state machine. +-- + cf_hold_proc: process( clk8, reset ) + begin + if reset = '1' then + cf_release <= '0'; + cf_count <= "0000"; + cf_hold_state <= hold_release_state; + elsif rising_edge( clk8 ) then + case cf_hold_state is + when hold_release_state => + cf_release <= '0'; + if cs8_cf = '1' then + cf_count <= "0011"; + cf_hold_state <= hold_request_state; + end if; + + when hold_request_state => + cf_count <= cf_count - "0001"; + if cf_count = "0000" then + cf_release <= '1'; + cf_hold_state <= hold_release_state; + end if; + when others => + null; + end case; + end if; + + end process; + +end; Index: System09_Trenz_TE0141/maisforth_rom0.vhd =================================================================== --- System09_Trenz_TE0141/maisforth_rom0.vhd (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom0.vhd (revision 105) @@ -0,0 +1,64 @@ + INIT_00 => x"F9E8FAB4FBDDFB0CFABAFA15FBCEFAA5FAE9F7A5F7FEFA7BFADFF8F0F85EF17E", + INIT_01 => x"00000200000000000000003000F3FB1F000000000003037AEA0FFDC1ED63FA61", + INIT_02 => x"003B00003B00003B00003B00000A000000000000000003000003000000000000", + INIT_03 => x"20375449584504020000846E0635011F45545543455845070200003B00003B00", + INIT_04 => x"0000B16E20370227063500008310455552542D4E4F2D544958450C040000B16E", + INIT_05 => x"4404040000B16E2037022606350000831045534C41462D4E4F2D544958450D04", + INIT_06 => x"6E101F063410352035203653454F444F4406040000B16E10362037211F455649", + INIT_07 => x"36EEC0BD3A4F44030400007EC03DCDD5C0BDEEC0BD52454F444F4406040000B1", + INIT_08 => x"05040000B16E101F06341035EEC0BD4554414552434F440804BEC0B16E203520", + INIT_09 => x"341035EEC0BD4E4F43434F4406040000B16E101F06341035EEC0BD5241564F44", + INIT_0a => x"4F440504E4C0B16E84EC06341035EEC0BD4E4F434F440504F8C0B16E1D84E606", + INIT_0b => x"EC06341035EEC0BD524156494F4406045DC1B16E84EC06341035EEC0BD4C4156", + INIT_0c => x"41564F440604CEC0B16E94EC06341035EEC0BD4C4156494F4406041FC1B16E84", + INIT_0d => x"1D5A012702845F00B0B606343F54494D45050285C0B16EE1E34958EEC0BD5352", + INIT_0e => x"552106060000B16E063501E7FA27028484A600B08E54494D4528050486C1B16E", + INIT_0f => x"2701845F00B0B606343F59454B04020000B16E063584A7558600B08E54524153", + INIT_10 => x"070468C0B16E4F01E6FA2701C484E600B08E063459454B0302F2C1B16E1D5A01", + INIT_11 => x"C4AE063424454E494C4E49070479C0B16EC4AF81ECC4AE063423454E494C4E49", + INIT_12 => x"C4AF853080E6C4AE063424454E494C4E492F08040000B16EC4AF3A10344F80E6", + INIT_13 => x"3500008310292846490404A1C0B16EA4AE1029284F544F47060434C2B16E0635", + INIT_14 => x"052706350000831029284F52455A4649080476C2B16E2231B16EA4AE10052606", + INIT_15 => x"A0E6063429432803040000B16EA1EC0634292802040000B16E2231B16EA4AE10", + INIT_16 => x"84E3A1AE29284F542B050467C2B16E063584EDA1AE29284F540404B8C2B16E1D", + INIT_17 => x"C2B16E063584ED0100C384EC0634A1AE292852434E4906041FC2B16E063584ED", + INIT_18 => x"05040000B16E063510368B300636E1A30080CC011F1036A1AE29284F440404C6", + INIT_19 => x"EC06342928504F4F4C060402C3B16EA4AE1006356232DD26E4A31029284F443F", + INIT_1a => x"504F4F4C2B070408C2B16E063546332231B16EA4AE100635C4ED09290100C3C4", + INIT_1b => x"33504F4F4C4E550602D6C2B16E20374433455641454C0502ACC2DE20C4E32928", + INIT_1c => x"0493C3B16E48A346EC06344A01029BC1B16E42A3C4EC0634490102AEC1B16E46", + INIT_1d => x"54060449C1250090C1BD47534D504F54060469C3230090C1BD434F56504F5406", + INIT_1e => x"444C480304BEC3290090C1BD41464E504F54060408C1270090C1BD584650504F", + INIT_1f => x"0090C1BD23534303041FC32D0090C1BD545845544E4F4307044DC22B0090C1BD", + INIT_20 => x"04E9C2330090C1BD45444F4D0404E8C3310090C1BD322D2347534D0604DDC12F", + INIT_21 => x"03048FC2370090C1BD53454D495423060478C3350090C1BD4E4F495443455307", + INIT_22 => x"0090C1BD45524548540504A0C33B0090C1BD424902045AC3390090C1BD424923", + INIT_23 => x"4D4948050636C3410090C1BD5245560306CDC33F0090C1BD524F48030633C13D", + INIT_24 => x"C3470090C1BD3F544F44040656C4450090C1BD4B4F020604C4430090C1BD4D45", + INIT_25 => x"BD4E493E030270C44B007BC1BD445257030420C4490090C1BD455245480402AF", + INIT_26 => x"C453007BC1BD4554415453050230C451007BC1BD45534142040271C14F007BC1", + INIT_27 => x"2705068AC458007BC1BD3249575327050613C455007BC1BD334957532705064B", + INIT_28 => x"C1BD4957532704060CC55E007BC1BD515249270406E2C45B007BC1BD51524946", + INIT_29 => x"C100C052C1BD4E494749524F06023FC464007BC1BD494D4E27040619C561007B", + INIT_2a => x"C37F3DC1BD544E45525255430704F0C4753DC1BD4B43415453444E49460904C5", + INIT_2b => x"0152C1BD3052020495C47E0152C1BD3053020433C5800052C1BD4249540304DC", + INIT_2c => x"070484C5FC0252C1BD305343030486C3000252C1BD465542594C460604A2C4FE", + INIT_2d => x"BD455552540402BBC4023DC1BD4C4C454304066EC57E3DC1BD455A4953424954", + INIT_2e => x"4C430704F8C3203DC1BD4C4202029FC5003DC1BD45534C41460502C7C4FF3DC1", + INIT_2f => x"0493C5B16EFE01CE522D5241454C430704AEC5B16E06357E01CE10532D524145", + INIT_30 => x"35011F21430202DDC5B16E301F06344050520304BAC5B16E401F063440505303", + INIT_31 => x"0635011F21320202C6C5B16E063584ED0635011F21010253C5B16E063584E706", + INIT_32 => x"0306D4C4B16E063584ED84E30635011F212B0202FEC4B16E063584ED063581ED", + INIT_33 => x"3584ED0100C384EC011F212B31030600C6B16E063584E784EB0635011F212B43", + INIT_34 => x"32020279C5B16E84EC011F40010242C5B16E4F84E6011F40430202F0C5B16E06", + INIT_35 => x"060DC6B16E10344F80E6011F544E554F43050272C6B16E103484AE81EC011F40", + INIT_36 => x"3706343E5202027CC4B16E06350636523E0202D3C5B16E103481EC011F2B4002", + INIT_37 => x"37063706343E52320302CEC6B16E0635063610361035523E3203029EC6B16E06", + INIT_38 => x"C4EC103442AE06344052320302C0C6B16EC4EC063440520202E6C6B16E103410", + INIT_39 => x"0225C7B16E4433504F52445232060608C7B16E4233504F5244520506DAC6B16E", + INIT_3a => x"04024FC7B16E10340634E4AE505544320402F7C6B16E06356232504F52443205", + INIT_3b => x"C7B16E66EC063466EC06345245564F3205025FC7B16E10346432103550494E32", + INIT_3c => x"5432050264C4B16E62AF62EC1037E4ED64AF64ECE4AE06365041575332050240", + INIT_3d => x"C088C7FBC688C7EAC6FFC0BD544F5232040232C77EC075C788C7FFC0BD4B4355", + INIT_3e => x"C6B16E0635504F5244040293C6B16E06340227000083105055443F0402AEC67E", + INIT_3f => x"504157530402AFC4B16E62EC06345245564F040286C6B16E0634505544030239", Index: System09_Trenz_TE0141/maisforth_rom1.vhd =================================================================== --- System09_Trenz_TE0141/maisforth_rom1.vhd (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom1.vhd (revision 105) @@ -0,0 +1,64 @@ + INIT_00 => x"AE544F52030282C7B16E1034E4EDE4AE4B43555404026FC7B16E101FE4EDE4AE", + INIT_01 => x"4E03020BC8B16EE4AFE4EC62ED62AE544F522D040226C5B16E62AF62ECE4EDE4", + INIT_02 => x"E4A3104E494D03025FC6B16E84EC3A411F584B43495004021BC8B16E62325049", + INIT_03 => x"A3104E494D5504061AC6B16E0635D02EE4A31058414D03024DC6B16E0635E02D", + INIT_04 => x"891F3C3002029DC7B16E0635AE22E4A31058414D5504062CC8B16E0635BF25E4", + INIT_05 => x"103E300202D6C7B16E5F4FB16E1D530426000083103D3002023EC8B16E891F1D", + INIT_06 => x"0202E2C7B16E5F4FD927E1A33D0102FBC7B16E891F431D891FB16E0226000083", + INIT_07 => x"3E55020269C8B16EEE26000083103E3C3003029BC8B16EFFFFCC0327E1A33E3C", + INIT_08 => x"4FC72DE1A33E010249C8B16E5F4FD422E1A33C5502028AC8B16E5F4FE225E1A3", + INIT_09 => x"02D2C8B16EE0E4E0A4444E4103020BC9B16E5F4FBA2EE1A33C0102EEC8B16E5F", + INIT_0a => x"545245564E49060279C8B16EE0E8E0A8524F58030226C9B16EE0EAE0AA524F02", + INIT_0b => x"A8C8B16EFA261F304958062784300635011F54464948534C060262C5B16E5343", + INIT_0c => x"45545942080681C9B16EFA261F305644062784300635011F5446494853520602", + INIT_0d => x"14C7B16E0100832D31020240C9B16E0100C32B310202C4C7B16E891E50415753", + INIT_0e => x"2D0102B6C9B16EE1E32B010259C9B16E56472F320202BCC8B16E49582A320202", + INIT_0f => x"19C9B16E4959101F063449580635011F2A3244030267C9B16E0100C35343E1A3", + INIT_10 => x"B16EE820442F3255440406AFC7B16E101F063456460635011F56472F32440302", + INIT_11 => x"06D5C9B16EEF2D4D5342410302EDC7B16E0100C3534345544147454E0602ECC9", + INIT_12 => x"011F1D5F063445544147454E4407029BC9B16EDD2D06354D45544147454E3F07", + INIT_13 => x"443F080633C9B16EE22D4D53424144040252CAB16EE1A31D00C2101F62ED62A3", + INIT_14 => x"8900C9101F62ED62E30635011F2B44020216CAB16ECF2D06354D45544147454E", + INIT_15 => x"C9B16E6632E4A3008200C264EC66ED62A366EC06342D44020201CAB16EE1E300", + INIT_16 => x"ED3D61E665A616342A4D55030259C8B16E008900C9063562ED62E32B4D0202DE", + INIT_17 => x"E33D64A6E4A7E4E649008661ED61E33DE4E665A661ED008962EB3D61E664A662", + INIT_18 => x"626963696469656810008E0634444F4D2F4D5506027DCAB16EE4AF643262AEE4", + INIT_19 => x"62AE534364ECE2261F306469656962ED0225E4A30620FE1C62EDE4A3082462EC", + INIT_1a => x"370635FA261F30A0E7062700008C303520364C4C49460402C1C9B16E643264AF", + INIT_1b => x"C20927A0A080A60F205FE4EDE4AE1062AF1062AE62E33E3C530306C2CAB16E20", + INIT_1c => x"AF1062AE62E345564F4D430502D4CAB16E30351DED26E4ACB16E303501CA1D00", + INIT_1d => x"3E45564F4D4306022AC6B16E06353035F826E4ACA0E780E60420E4EDE4AE1062", + INIT_1e => x"343F31B16E06353035F726E4AC10A2E782E60420AB31E4AE1062AF108B3062AE", + INIT_1f => x"F8261F30E126A0E1082700008C3035203650494B53040666CBB16E101F203720", + INIT_20 => x"02FDC8C220F8261F30C627A0E1082700008C303520364E4143530406ABC9DD20", + INIT_21 => x"4F423E0502DFC8B16E0100C32B52414843050220CCB16E0200C32B4C4C454305", + INIT_22 => x"00832D5241484305064ACCB16E0200832D4C4C4543050694CBB16E0300C35944", + INIT_23 => x"74CCB16E4958534C4C454305022ECCB16E0300833E59444F42050690CAB16E01", + INIT_24 => x"52040266CCB16E0300834B4E494C3E454D414E090423CAB16E53524148430503", + INIT_25 => x"CBC97EC0DBC7C0CB7ACCAEC9DDC626CCE6C704C64EC80BC7D1C6FFC0BD4C4C4F", + INIT_26 => x"00DCC2FFC0BD544F4C4C41050258CC7EC0D7C940BCC2A7C4FFC0BD4441500302", + INIT_27 => x"FFC0BD2C430202EACB7EC04900DCC2B3C52CC6A7C4FFC0BD2C01024CC97EC049", + INIT_28 => x"CCB16E101F85301FC480E6011F3E454D414E0506A8CA7EC04900F0C21DC6A7C4", + INIT_29 => x"FFC0BD52454F4421050481CCB16E101FFA2682E460C6011F454D414E3E0506E6", + INIT_2a => x"040DCDB16E1D5A5801C482E6011F4D4D494004049ECC7EC02CC6AEC913CDD4C3", + INIT_2b => x"CCB16E1D7EC482E6011F434F5640040460CDB16E891F1D82E6011F3F4D4F4804", + INIT_2c => x"0405CCB16E1D5A012400C6E1A3E4AFE1A362EC011FE4A34E49485449570602FA", + INIT_2d => x"BD53433E0304C1CC7EC0E0C937C97CBCC2C4C97ACCFCC397C5FFC0BD50534303", + INIT_2e => x"00DCC2FFBCC2A1C6A4CDFFC0BD3E5343030482CD7EC03CC6A4CD2F00F0C2FFC0", + INIT_2f => x"C2DDC6D3CD2F00DCC22ACAD1C6FCC3FFC0BD4B4349502D5343070240CA7EC02F", + INIT_30 => x"26CE25C300BCC20BC7D1C6FFC0BD4C4C4F522D53430702B9CB7EC0BFCD2F00CB", + INIT_31 => x"CE7EC0BFCDFBC633CE3DC3BFCD39CE25C300BCC2EAC6D3CDDDC620CE3DC3D3CD", + INIT_32 => x"38CAF2C738CAF2C7FFC0BD2A4D020237CDB16E891F1D891F0634443E5303020A", + INIT_33 => x"C775CAD1C6D1C6F2C7FFC0BD4D45522F4D53060252CE7EC086CA50C988C7D8CA", + INIT_34 => x"4F4D2F4D46060271CD7EC000C848CADDC600C848CA50C90BC7DDC613CB38CA0B", + INIT_35 => x"9EC850C90BC71FC800C848CA0BC700C813CB38CA0BC775CA10C8D1C6FFC0BD44", + INIT_36 => x"BD2A01024DCD7EC02BC700C8E0C91FC80BC7B9C9D6CE7BC2F2C72ACAD6CE7BC2", + INIT_37 => x"020CCB7EC0A1CEDDC646CED1C6FFC0BD444F4D2F040242CE7EC0DBC755CEFFC0", + INIT_38 => x"2A05029ACE7EC0DBC7F0CEFFC0BD444F4D0302E6CD7EC042C8F0CEFFC0BD2F01", + INIT_39 => x"7EC042C824CFFFC0BD2F2A02028CCC7EC0A1CEDDC655CED1C6FFC0BD444F4D2F", + INIT_3a => x"C10DBCC2FFC0BD52430202A0CD7EC03F00F0C2CBC1FFC0BD54494D450402D4CC", + INIT_3b => x"D6C5FFC0BD4543415053050243CF7EC04100F0C23F00CBC2CCC5CBC10ABCC2CB", + INIT_3c => x"48CFE6C7A4CF25C300BCC200C8D6C5FFC0BD534543415053060275CF7EC048CF", + INIT_3d => x"3DC348CFB4C6C2CF25C300BCC2FFC0BD45505954040249CB7EC0DBC79CCF3DC3", + INIT_3e => x"CBC2CCC53F00CBC2CCC548CF0CBCC2FFC0BD454741500402DDCE7EC0DBC7BACF", + INIT_3f => x"C1F2C7D6C508BCC2AFC068C4FFC0BD45434150534B434142090634CF7EC04100", Index: System09_Trenz_TE0141/maisforth_rom2.vhd =================================================================== --- System09_Trenz_TE0141/maisforth_rom2.vhd (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom2.vhd (revision 105) @@ -0,0 +1,64 @@ + INIT_00 => x"0CC2FFC0BD474E49545045434341090434CA7EC03F00DCC2FFBCC2CBC1CBC1CB", + INIT_01 => x"D4C808BCC27EC0DBC764C73BD07BC2D4C8F2C70DBCC254D07BC228C9D6C5E6C7", + INIT_02 => x"D07BC2D4C84EC804BCC2F2C7D6C51ED06EC2B9C9F1CF4ED07BC2E6C752D07BC2", + INIT_03 => x"504543434106026DCE1ED06EC2AEC948CF1DC6D7C975C7E6C71ED06EC2DBC767", + INIT_04 => x"CB00C8CCC510C8FFC0BD444F4D2F55440606BBCD7EC01BD0CCC500C8FFC0BD54", + INIT_05 => x"C6D8CAD1C6DBC7D8CA10C8FFC0BD2A55440306E7CF7EC0DDC613CB00C8D1C613", + INIT_06 => x"0270CA7EC01DC6E0C32B00DCC2FFBCC2FFC0BD444C4F48040222CD7EC0D7C9DD", + INIT_07 => x"09BCC2E6C7FFC0BD54494749443E0604ABCF7EC02B00CBC2C5CCFFC0BD233C02", + INIT_08 => x"1FC896D095C6CCC4FFC0BD2301027AD07EC0D7C930BCC2D7C937C907BCC21BC9", + INIT_09 => x"230202EBCE7EC02FD198C243C954C715D1FFC0BD5323020287CF7EC0CDD0F8D0", + INIT_0a => x"C2AFC09EC8FFC0BD4E474953040256CF7EC0E0C9F2C7C5CCE0C346C7FFC0BD3E", + INIT_0b => x"C9CF7EC041D12CD1E3D0FFC0BD474E495254532E55440906F1D07EC0CDD02DBC", + INIT_0c => x"06AED07EC041D158D11FC82CD1E3D075CA10C8FFC0BD474E495254532E440806", + INIT_0d => x"D1FFC0BD2E554403068FD07EC0B0CF8ECFE0C95DC854C7FFC0BD455059545205", + INIT_0e => x"0202CAD17EC0A6D1DDC673D1D1C6FFC0BD522E55440406C8D07EC07BCFB0CF73", + INIT_0f => x"021ECF7EC0BCD100BCC2FFC0BD2E55020213D17EC07BCFB0CF8AD1FFC0BD2E44", + INIT_10 => x"D17EC0A6D1DDC68AD1D1C6FFC0BD522E440302A0D17EC0E2D146CEFFC0BD2E01", + INIT_11 => x"C6FFC0BD522E0202E0D07EC0A6D1DDC673D100BCC2D1C6FFC0BD522E55030229", + INIT_12 => x"4345440702DFD17EC002D295C6FFC0BD3F010200CF7EC0A6D1DDC68AD146CED1", + INIT_13 => x"C6CCC410BCC2FFC0BD5845480302B8D17EC02CC6CCC40ABCC2FFC0BD4C414D49", + INIT_14 => x"554F530602F0D17EC02CC6CCC402BCC2FFC0BD5952414E494206063CCC7EC02C", + INIT_15 => x"AFE4EC62ED62E3011F474E495254532F070222D27EC043C44EC4FFC0BD454352", + INIT_16 => x"435441432906049CD2B16E10365E304036284843544143060411D0B16EE1A3E4", + INIT_17 => x"0469D17EC0E1D270C0CFD2FFC0BD484354414305023ED1B16E5F4F0634443348", + INIT_18 => x"524F42410502AFD2B16E2037101F4037F926C1A310301F011F574F5248542806", + INIT_19 => x"6E20C002227AC1062561C1524550505528060473D27EC007D3FFBCC2FFC0BD54", + INIT_1a => x"AEC91DC6F2C735D389C6E6C764D325C300BCC2FFC0BD524550505505064ED2B1", + INIT_1b => x"7EC8D1C6E0C954C71FC8FFC0BD455241504D4F43070244D37EC0DBC754D33DC3", + INIT_1c => x"4F4D0402ECD27EC0AEC9C4C9BFC8AFC0E6C7DDC67EC02BC78CD37BC2C9C76ACB", + INIT_1d => x"414C50050600D37EC0C0CB7EC09ACBB5D37BC289CD75C7D7C954C7FFC0BD4556", + INIT_1e => x"A3D2D1C6FFC0BD44524F57040253D17EC0A2D300C834CC1DC654C7FFC0BD4543", + INIT_1f => x"3CC6B3C454C7E0C9F2C7D1C60ACCDDC600C8F2C7EFCB0BC710C8B7D295C6BFC4", + INIT_20 => x"BD45535241500502BCD37EC0A7C450C6BFC4E0C9D7C9F2C8E6C7DDC6C2D3A7C4", + INIT_21 => x"BFC4E0C9D7C9F2C8E6C7DDC6EAC60ACCDDC654C7B7D295C6BFC4A3D2D1C6FFC0", + INIT_22 => x"C6B16E0635042B5D401F06344B434154533F0606DAD27EC0E0C9F2C7DDC650C6", + INIT_23 => x"CD49BCC202BCC295C6CCC4FFC0BD455341423F05064DD407D37E1D5C01264DFC", + INIT_24 => x"D3EABCC292C0D4C8FFC0BD524941503F0506D4D37EC007D3C2BCC264D292C089", + INIT_25 => x"0802A6D47EC007D3F2BCC292C095C6DAC4FFC0BD504D4F433F0506C8D27EC007", + INIT_26 => x"4D4F4309046BD37EC04900DCC2B3C52CC6A7C4ACD4FFC0BD2C454C49504D4F43", + INIT_27 => x"CD7EC02CC6DAC4CCC5FFC0BD5B01030ECF7EC0C8D427C2FFC0BD2928454C4950", + INIT_28 => x"FFC0BD45524548542D454641530A046CD47EC02CC6DAC4BFC5FFC0BD5D0102CF", + INIT_29 => x"594C46050400D27EC05CC43D00CBC28BC535D57BC20EC9E0C98BC55CC440BCC2", + INIT_2a => x"C004D5EAC6DDC64900CBC2E6C73D00CBC2A7C41DD592C095C6DAC4FFC0BD5245", + INIT_2b => x"FFC0BD2953282204045CD27EC03D00CBC24900CBC25CC4A7C4F4D47EC0E6D4C3", + INIT_2c => x"C2FFC0BD282E02033CD57EC0B0CF3CC2FFC0BD295328222E050486D27EC03CC2", + INIT_2d => x"78D57EC0DACCAEC989C6D9D3FFC0BD2C44524F570506BFD47EC0B0CF1FD429BC", + INIT_2e => x"4F424109049DD37EC0C2D3DACCAEC9F2C7A7C41FD4FFC0BD2C45535241500606", + INIT_2f => x"06031BD37EC056C207D3FEBCC23100CBC20BC7F8D57BC2FFC0BD295328225452", + INIT_30 => x"42D5FFC0BD22010739D27EC0C8D522BCC2E6D5E6D442D5FFC0BD2254524F4241", + INIT_31 => x"42D5FFC0BD222E020319D61ED66EC2FFC0BD225302038FD40FD66EC27DD5E6D4", + INIT_32 => x"00CBC2E8CCB6C3E8CC00C8A7C4FFC0BD2247534D0406F2D40FD66EC28DD5E6D4", + INIT_33 => x"0438D67EC0CEC9E0C900C871C504C6FFC0BD48545045440502C1D50FD66EC225", + INIT_34 => x"45444F4D54494E49080402D57EC089CD8000AFC280BCC2FFC0BD3F5449423805", + INIT_35 => x"C1BCC2AFC0FFC0BD4C4147454C4C493F0804DCD57EC03300CBC230BCC2FFC0BD", + INIT_36 => x"BCC2B9C900C83300CBC220BCC2FFC0BD4745525845444E490804AFD67EC007D3", + INIT_37 => x"BCC2FFC0BD45444F4347455207042ED37EC043C96EC905BCC2B8D60EC9F2C703", + INIT_38 => x"4040201006040200535559584442412C107DD5D1C6E0C937C9D6C528C9F2C75A", + INIT_39 => x"45444F4D2B0504DCD407D3C1BCC27EC089C6D7C932D77BC20ACCDDC610C8CEC9", + INIT_3a => x"040ED27EC037C90FBCC292C0E2C850BCC237C9F000AFC2E6C7D7C918C4FFC0BD", + INIT_3b => x"AFC200C88AD77BC286D6E6C7E0C9D7C902BCC2A7C400C8FFC0BD4C4552435005", + INIT_3c => x"C0BD544553464F43060497D67EC0E8CCFDCC00C8B9C97EC0FDCCFDCC37C9FE00", + INIT_3d => x"10BCC2F0BCC2F2C77EC0DBC7FDCC43C904BCC237C9F000AFC2B8D798C2F2C7FF", + INIT_3e => x"CC43C937C91FBCC200C837C960BCC2E3D77BC237C9ABC837C910BCC2F2C789CD", + INIT_3f => x"04FFD57EC0E8CCFDCC7EC0FDCCFDCC37C9FE00AFC2F7D77BC286D6F2C77EC0FD", Index: System09_Trenz_TE0141/maisforth_rom3.vhd =================================================================== --- System09_Trenz_TE0141/maisforth_rom3.vhd (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom3.vhd (revision 105) @@ -0,0 +1,64 @@ + INIT_00 => x"C725D87BC2D4C88900AFC2E6C737C98F00AFC2E6C7FFC0BD44455845444E4907", + INIT_01 => x"C2D4C88F00AFC2E6C77EC066D7DBC737D87BC2D4C88D00AFC2E6C77EC09ED7DB", + INIT_02 => x"C989C6FFC0BD44454D4D4905043AD77EC0FDCCDBC77EC0E8CCFDCCDBC74BD87B", + INIT_03 => x"D5C0BDEEC0BD5845534F44050468D67EC0FDCC7EC0E8CC6DD87BC2B8D646CEB9", + INIT_04 => x"7EC0A0D6E8CC95C6D5C0BDEEC0BD324957534F44060487D57EC0A0D6FDCC89C6", + INIT_05 => x"ABD57EC0A0D6FDCCFDCC89C6B8D618C4D5C0BDEEC0BD494157434F44060419D4", + INIT_06 => x"7EC05AD8DBC7E0D87BC2D4C800BCC2E6C7A0D618C4FFC0BD5244414E45470604", + INIT_07 => x"DBC706D97BC2D4C820BCC2E6C77EC0FDCCDBC7DBC7F3D87BC2D4C810BCC2E6C7", + INIT_08 => x"04A3D87EC0B8D67EC0E8CCDBC7DBC719D97BC2D4C830BCC2E6C77EC008D8DBC7", + INIT_09 => x"BD59444C4F44050480D67EC0C8D8FDCC40D7B4C6D5C0BDEEC0BD47454E4F4405", + INIT_0a => x"89C6D5C0BDEEC0BD4758454F44050420D97EC0C8D8E8CC40D7C3C6D5C0BDEEC0", + INIT_0b => x"D5C0BDEEC0BD41454C4F44050439D97EC0A0D6FDCCD7C96EC904BCC200C8FDCC", + INIT_0c => x"BDEEC0BD5145424F44050474D97EC0A0D608D8FDCC89C6B8D6E0C920BCC218C4", + INIT_0d => x"C0FDCCFDCC00C8C1D97BC286D6E6C7A0D6E0C9D7C902BCC2A7C400C889C6D5C0", + INIT_0e => x"BDEEC0BD4152424F44050496D97EC0E8CCE0C902BCC2FDCC00C8FDCC10BCC27E", + INIT_0f => x"CCFDCCA4C900C803DA7BC286D6E6C7A0D6E0C9D7C902BCC2A7C400C895C6D5C0", + INIT_10 => x"C0D0D689C6D5C0BDEEC0BD292D4F44040499D57EC0E8CCB9C9FDCC00C87EC0FD", + INIT_11 => x"52534C0308F3D6004329D9BD4D4F43030854D8004029D9BD47454E030860D77E", + INIT_12 => x"0830DA004729D9BD52534103084BD6004629D9BD524F52030881D1004429D9BD", + INIT_13 => x"4929D9BD4C4F52030810DA004829D9BD4C534C03088BD8004829D9BD4C534103", + INIT_14 => x"545354030874D8004C29D9BD434E49030897D7004A29D9BD434544030852D900", + INIT_15 => x"0812D5004F29D9BD524C430308C1D8004E29D9BD504D4A030878DA004D29D9BD", + INIT_16 => x"BD414342530408CDDA018129D9BD41504D430408C0DA018029D9BD4142555304", + INIT_17 => x"9CDA018429D9BD41444E41040890DA028329D9BD444255530408B4DA018229D9", + INIT_18 => x"D9BD415453030800D8018629D9BD41444C0308D6D9018529D9BD415449420408", + INIT_19 => x"08DADA018929D9BD414344410408F4DA018829D9BD41524F450408C7D6008729", + INIT_1a => x"D9BD58504D4304084CDB018B29D9BD41444441040833DB018A29D9BD41524F03", + INIT_1b => x"5303082BD6028E29D9BD58444C030801DB008D29D9BD52534A03080EDB028C29", + INIT_1c => x"C129D9BD42504D4304088ADB01C029D9BD42425553040826DB008F29D9BD5854", + INIT_1d => x"41040860DA02C329D9BD44444441040854DA01C229D9BD42434253040897DB01", + INIT_1e => x"C629D9BD42444C03083CDA01C529D9BD425449420408A8DA01C429D9BD42444E", + INIT_1f => x"44410408BEDB01C829D9BD42524F45040840DB00C729D9BD4254530308E7DA01", + INIT_20 => x"01CB29D9BD424444410408FDDB01CA29D9BD42524F0308A4DB01C929D9BD4243", + INIT_21 => x"BD55444C030848DA00CD29D9BD44545303080ADC02CC29D9BD44444C03086CDA", + INIT_22 => x"F0DB02831042D9BD44504D430408E4DB00CF29D9BD555453030816DC02CE29D9", + INIT_23 => x"59545303081ADB028E1042D9BD59444C030866DB028C1042D9BD59504D430408", + INIT_24 => x"00CF1042D9BD5354530308B1DB02CE1042D9BD53444C0308CBDB008F1042D9BD", + INIT_25 => x"040824DA028C1142D9BD53504D43040847DC02831142D9BD55504D43040896DC", + INIT_26 => x"327DD9BD5341454C04083BDC317DD9BD5941454C040884DA307DD9BD5841454C", + INIT_27 => x"D9BD5246540308BFDC1E5BD9BD47584503082FDC337DD9BD5541454C040889DC", + INIT_28 => x"4141440308D7DC137DD8BD434E59530408B1DC127DD8BD504F4E03086FDC1F5B", + INIT_29 => x"424103087CDC397DD8BD535452030823DC1D7DD8BD58455303087EDB197DD8BD", + INIT_2a => x"5303083DDD3D7DD8BD4C554D0308A3DC3B7DD8BD4954520308FADC3A7DD8BD58", + INIT_2b => x"CBDC437DD8BD414D4F43040861DC407DD8BD4147454E040848DD3F7DD8BD4957", + INIT_2c => x"D8BD41525341040859DB467DD8BD41524F52040872DB447DD8BD4152534C0408", + INIT_2d => x"4F5204088DDD487DD8BD414C534C040881DD487DD8BD414C5341040899DD477D", + INIT_2e => x"C9DD4C7DD8BD41434E49040853DC4A7DD8BD414345440408E3DC497DD8BD414C", + INIT_2f => x"D8BD4247454E04081CDD4F7DD8BD41524C43040875DD4D7DD8BD415453540408", + INIT_30 => x"4F520408E1DD547DD8BD4252534C040832DD537DD8BD424D4F430408EFDC507D", + INIT_31 => x"11DE587DD8BD424C5341040829DE577DD8BD42525341040810DD567DD8BD4252", + INIT_32 => x"D8BD424345440408BDDD597DD8BD424C4F5204081DDE587DD8BD424C534C0408", + INIT_33 => x"4C43040805DE5D7DD8BD42545354040859DE5C7DD8BD42434E4904085EDD5A7D", + INIT_34 => x"3F1195D8BD33495753040835DE3F1095D8BD3249575304087DDE5F7DD8BD4252", + INIT_35 => x"48535004084DDE1CADD8BD4343444E410508A5DD1AADD8BD4343524F040853DD", + INIT_36 => x"08D4DE36ADD8BD554853500408F9DD35ADD8BD534C55500408BCDE34ADD8BD53", + INIT_37 => x"20DFD9BD415242030869DD3CADD8BD494157430408EDDD37ADD8BD554C555004", + INIT_38 => x"BD4948420308F8DE219FD9BD4E5242030805DD178DDFD9BD5253420308E0DE16", + INIT_39 => x"4F4C42030871DE249FD9BD534842030826DF239FD9BD534C42030841DE229FD9", + INIT_3a => x"4E420308D8DB259FD9BD534342030847DF249FD9BD434342030831DF259FD9BD", + INIT_3b => x"42030873DF289FD9BD435642030852DF279FD9BD51454203081BDF269FD9BD45", + INIT_3c => x"03085DDF2B9FD9BD494D42030868DF2A9FD9BD4C50420308C8DE299FD9BD5356", + INIT_3d => x"089FDF2E9FD9BD5447420308AADF2D9FD9BD544C42030889DF2C9FD9BD454742", + INIT_3e => x"ECDE243DC1BD3F3C550308CBDF233DC1BD3F3E55030889DE2F9FD9BD454C4203", + INIT_3f => x"10DF283DC1BD3F53560308C0DF263DC1BD3F3D0208D5DD243DC1BD3F53430308", Index: System09_Trenz_TE0141/maisforth_rom4.vhd =================================================================== --- System09_Trenz_TE0141/maisforth_rom4.vhd (nonexistent) +++ System09_Trenz_TE0141/maisforth_rom4.vhd (revision 105) @@ -0,0 +1,64 @@ + INIT_00 => x"0816E02F3DC1BD3F3E02087EDF2C3DC1BD3F3C020804DF2A3DC1BD3F3C300308", + INIT_01 => x"DD013DC1BD58010894DF003DC1BD44010820E07EC050C901BCC2FFC0BD4F4E02", + INIT_02 => x"43500208B1DD043DC1BD530108E1DF033DC1BD550108ECDF023DC1BD59010827", + INIT_03 => x"3DC1BD52434303084BE0093DC1BD42010801E0083DC1BD410108D6DF053DC1BD", + INIT_04 => x"8118DABD2B2B290308AFDE8018DABD2B29020867E00B3DC1BD5044020839E00A", + INIT_05 => x"30E08418DABD29010842E08318DABD292D2D030898E08218DABD292D02088EE0", + INIT_06 => x"0C040CE08B18DABD294402085DE08618DABD2941020879E08518DABD29420208", + INIT_07 => x"023CDF7EC02029028DD5C3C02820028DD5FFC0BD455A49534548544E45524150", + INIT_08 => x"12E198C2E6C7B9C902D24EC8E6C76ED6AFC06ED67BCFECE054D4FFC0BD532E02", + INIT_09 => x"F3D14EC8E6C76ED6AFC06ED67BCFECE054D4FFC0BD532E550306B8E07EC0DBC7", + INIT_0a => x"7BC20EC9F2C7FDBCC2FFC0BD47534D2E040600E17EC0DBC73AE198C2E6C7B9C9", + INIT_0b => x"7BC295C6E6C795C626CC7AE16EC2B6C37EC0B0CFB4C60BC47BCFAFC0AEC970E1", + INIT_0c => x"73654D0A8DD5ECE0AFC0C9C7B0CFB4C626CC26CC76E17BC2D4C895C654C78CE1", + INIT_0d => x"BCC28DC454D472D4FFC0BD4B4F2E0304F6DF7EC03CD200BCC220232065676173", + INIT_0e => x"CF4B4F20038DD5DFE16EC26B6F20038DD5D9E17BC295C6DAC4DFE17BC237C901", + INIT_0f => x"C42BE1FFE17BC237C904BCC28DC4FFE16EC203E1F2E17BC237C902BCC28DC459", + INIT_10 => x"3CD200BCC264D2E6C795C6CCC492C0D4C895C6CCC40ABCC2AFC037C908BCC28D", + INIT_11 => x"C53B00CBC2E6C766C5FFC0BD59524555510502A3E07EC02029028DD52CC6CCC4", + INIT_12 => x"C5FFC0BD4C4C49464552060270E07EC07BCF2CC6BFC400BCC23900CBC281D0A7", + INIT_13 => x"C0BD3E44524F57050627E17EC0CCC57EC0BFC534E2B5E171E27BC2D4C84EC466", + INIT_14 => x"07D3F0BCC2A0E298C25CE2D1C6DBC77EC042C891E27BC289C6E6C7D9D3E6C7FF", + INIT_15 => x"CB580FC401E85886E858891F84A6011F4441455248540604B1E181E26EC2DDC6", + INIT_16 => x"54C75DC820BCC2AEC989C6E6C7FFC0BD454D414E444E4946080484E0B16E1D03", + INIT_17 => x"42C8EAE298C26ACB75C7E6C7FEE27BC2E6C795C696CCECE26EC2B0E2F2C74AD3", + INIT_18 => x"C200C8CCC563E37BC2E6C7EAC6FFC0BD44524F57444E49460804D5E07EC042C8", + INIT_19 => x"E37BC2D1C6E0C9F2C7DDC642C80ACC76CD42C875C718C795C650CC96CC29E36E", + INIT_1a => x"C813CDE6C742C863E37BC2E6C7DBC723E398C237C90BC765CDE6C7E6C742C845", + INIT_1b => x"F2C75BC5F0C3AFC0E6C7D0E2E6C7FFC0BD444E4946040207E37EC039C752CD00", + INIT_1c => x"A7C4D1C6FFC0BD5453494C44524F572D4843524145530F022EE27EC010E3E0C9", + INIT_1d => x"C0E6C710E301BCC21DC610C813CDA7C4C3E37BC2F2C7DDC6D0E2E6C7A7C4C2D3", + INIT_1e => x"7EC03500CBC2A7C4FFC0BD4E4F495443455321080465DE7EC042C8DBC7CCC592", + INIT_1f => x"E8CCAFC2E6D404E47BC289CD80BCC28000AFC2E6C7FFC0BD2C54494C0404A9E2", + INIT_20 => x"95C6DAC4FFC0BD4C41524554494C0703C1E07EC0D5E3FDCCBCC2E6D47EC0D5E3", + INIT_21 => x"E3E8E300C8AFC095C6DAC4FFC0BD4C41524554494C320803DFE07EC0E8E3AFC0", + INIT_22 => x"FFC0BD3E544947494406064FE17EC04500CBC2FFC0BD4B4F3E0306E3E37EC0E8", + INIT_23 => x"C296E47BC20EC9F2C710BCC284E47BC20EC9F2C709BCC2E0C930BCC20BC7D1C6", + INIT_24 => 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x"65520B8DD559CFB7E77BC2DDC600BCC22CC6C0CBAEC989C6F2C7A7C4E6C7DACC", + INIT_3d => x"C7A7C41DC6B9C9A7C443C98000AFC27BCFB0CFB4C6A7C420676E696E69666564", + INIT_3e => x"C989C6F2C789C65BC5B9C9A7C42CC600C8A7C42CC696CCA7C495C6E6C7B0E2E6", + INIT_3f => x"4304045FE77EC0D5E311C16ADBCCC5DACCAEC989C62900CBC2A7C41DC600C843", Index: System09_Trenz_TE0141/fep_toplevel_hans.vhd =================================================================== --- System09_Trenz_TE0141/fep_toplevel_hans.vhd (nonexistent) +++ System09_Trenz_TE0141/fep_toplevel_hans.vhd (revision 105) @@ -0,0 +1,986 @@ +-- SECD Front End Processor derived from System09 written by John E. Kent +-- This core adheres to the GNU public license + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; +--use config.all; + +entity secd_fep_trenz is + port( + utmi_clkout : in Std_Logic; -- UTMI Clock input + utmi_databus16_8 : out Std_Logic; -- UTMI configuration input + + reset_sw : in Std_logic; -- Master Reset input (active low) + + -- PS/2 Keyboard + ps2_clk1 : inout Std_logic; + ps2_data1 : inout Std_Logic; + + -- Uart Interface + fpga_rxd : in Std_Logic; + fpga_txd : out Std_Logic; + fpga_cts : in Std_Logic; + fpga_rts : out Std_Logic; + + -- CRTC output signals + vsync_b : out Std_Logic; + hsync_b : out Std_Logic; + fpga_b : out Std_Logic_Vector(2 downto 0); + fpga_g : out Std_Logic_Vector(2 downto 0); + fpga_r : out Std_Logic_Vector(2 downto 0); + + -- LEDS & Switches + mm_led : out Std_Logic; + led : out Std_Logic_Vector(3 downto 0); + + joy_down : in Std_Logic; + joy_fire : in Std_Logic; + joy_left : in Std_Logic; + joy_right : in Std_Logic; + joy_up : in Std_Logic; + + -- LCD Display + lcd_e : out Std_Logic; + lcd_rw : out Std_Logic; + lcd_rs : out Std_Logic; + lcd_d : out Std_Logic_Vector(3 downto 0); + + -- Audio + aud_out : out std_logic_vector(4 downto 1); + + -- Memory interface + ram_a : out std_logic_vector(20 downto 1); + ram_io : inout std_logic_vector(15 downto 0); + ram_bhen : out std_logic; + ram_blen : out std_logic; + ram_cen : out std_logic; + ram_oen : out std_logic; + ram_wen : out std_logic; + + -- Compact flash + cf_reset : out std_logic; +-- cf_irq : in std_logic; + cf_iord : out std_logic; + cf_iowr : out std_logic; +-- cf_wait : in std_logic; +-- cf_dasp : in std_logic; +-- cf_pdiag : in std_logic; +-- cf_cd1 : in std_logic; +-- cf_cd2 : in std_logic; +-- iois16 : in std_logic; +-- cf_oe : out std_logic; + cf_pwr_en : out std_logic; + cf_cs0 : out std_logic; + cf_cs1 : out std_logic +-- cf_we : out std_logic; +-- cf_rew : out std_logic + ); +end secd_fep_trenz; + +------------------------------------------------------------------------------- +-- Architecture for System09 +------------------------------------------------------------------------------- +architecture rtl of secd_fep_trenz is + ----------------------------------------------------------------------------- + -- constants + ----------------------------------------------------------------------------- + constant fep_only : integer := 1; + + constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock + constant VGA_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock + constant CPU_Clock_Frequency : integer := 12500000; -- CPU Clock + constant BAUD_Rate : integer := 57600; -- Baud Rate + constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16; + + ----------------------------------------------------------------------------- + -- ChipScope Pro components and signals + ----------------------------------------------------------------------------- + +-- component icon +-- port(control0 : out std_logic_vector(35 downto 0)); +-- end component; + +-- component ila +-- port(control : in std_logic_vector(35 downto 0); +-- clk : in std_logic; +-- trig0 : in std_logic_vector(39 downto 0)); +-- end component; + +-- signal chipscope_control : std_logic_vector(35 downto 0); +-- signal ila_clock : std_logic; + + ----------------------------------------------------------------------------- + -- Signals + ----------------------------------------------------------------------------- + + -- Clocks + attribute buffer_type : string; + attribute period : string; + + signal vdu_clk : std_logic; -- 25 Mhz + attribute period of vdu_clk : signal is "40 ns"; + attribute buffer_type of vdu_clk : signal is "BUFG"; + + signal cpu_clk : std_logic; -- 12.5 Mhz + attribute buffer_type of cpu_clk : signal is "BUFG"; + + -- BOOT ROM + signal rom_cs : Std_logic; + signal rom_data_out : Std_Logic_Vector(7 downto 0); + + -- RAM + signal user_ram0_cs : std_logic; + signal user_ram0_dout : std_logic_vector(7 downto 0); + signal user_ram1_cs : std_logic; + signal user_ram1_dout : std_logic_vector(7 downto 0); + + -- UART Interface signals + signal uart_data_out : Std_Logic_Vector(7 downto 0); + signal uart_cs : Std_Logic; + signal uart_irq : Std_Logic; + signal baudclk : Std_Logic; + signal DCD_n : Std_Logic; + signal RTS_n : Std_Logic; + signal CTS_n : Std_Logic; + + -- keyboard port + signal keyboard_data_out : std_logic_vector(7 downto 0); + signal keyboard_cs : std_logic; + signal keyboard_irq : std_logic; + + -- CPU Interface signals + signal cpu_rw : std_logic; + signal cpu_vma : std_logic; + signal cpu_halt : std_logic; + signal cpu_hold : std_logic; + signal cpu_firq : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + + -- Compact Flash port + signal cf_data_out : std_logic_vector(7 downto 0); + signal cf_cs : std_logic; + signal cf_rd : std_logic; + signal cf_wr : std_logic; + + -- Video Display Unit + signal vdu_cs : std_logic; + signal vdu_data_out : std_logic_vector(7 downto 0); + + -- VGA output signals (distributed to VGA DAC) + signal red : std_logic; + signal green : std_logic; + signal blue : std_logic; + + -- System Reset (generated by key press) + signal reset : std_logic; + + -- LCD register select + signal lcd_cs : std_logic; + + -- LED register select + signal led_cs : std_logic; + signal led_reg : std_logic_vector(7 downto 0) := (others => '0'); + + -- Joystick buffer + signal joystick : std_logic_vector(7 downto 0); + + -- LED Flasher + signal blink_count : std_logic_vector(25 downto 0) := (others => '0'); + + -- SECD interface + signal secd_button : std_logic := '0'; + signal secd_stop : std_logic := '1'; + signal secd_stopped : std_logic := '1'; + signal secd_state : std_logic_vector(1 downto 0); + signal secd_ram_addr_hi : std_logic_vector(7 downto 0) := (others => '0'); + signal secd_ram_addr_high_cs : std_logic := '0'; + signal secd_ram_cs : std_logic := '0'; + signal secd_control_cs : std_logic := '0'; + + -- SECD RAM Controller interface + signal secd_ram_busy : std_logic; + + -- RAM signal taps + signal ram_bhenx : std_logic; + signal ram_blenx : std_logic; + signal ram_cenx : std_logic; + signal ram_oenx : std_logic; + signal ram_wenx : std_logic; + + -- Interface signals for SECD + signal secd_ram_din32 : std_logic_vector(31 downto 0); + signal secd_ram_dout32 : std_logic_vector(31 downto 0); + signal secd_ram_addr32 : std_logic_vector(13 downto 0); + signal secd_ram_read32 : std_logic; + signal secd_ram_write32 : std_logic; + + -- Interface signals for 6809 + signal secd_ram_dout8 : std_logic_vector(7 downto 0); + signal secd_ram_hold : std_logic; + + -- Locked signal of clock synthesizer + signal clock_locked : std_logic; + signal ila_clock :std_logic; +----------------------------------------------------------------- +-- +-- CPU09 CPU core +-- +----------------------------------------------------------------- + + component cpu09 + port ( + clk : in std_logic; + rst : in std_logic; + rw : out std_logic; -- Asynchronous memory interface + vma : out std_logic; + address : out std_logic_vector(15 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + halt : in std_logic; + hold : in std_logic; + irq : in std_logic; + nmi : in std_logic; + firq : in std_logic + ); + end component; + + +---------------------------------------- +-- +-- 16KByte Block RAM Mais Forth ROM +-- +---------------------------------------- + component maisforth_rom_16k + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (13 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); + end component; + +---------------------------------------- +-- +-- 8KBytes Block RAM for FLEX9 +-- $C000 - $DFFF +-- +---------------------------------------- + component ram_2k + Port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector (12 downto 0); + rdata : out std_logic_vector (7 downto 0); + wdata : in std_logic_vector (7 downto 0) + ); + end component; + +----------------------------------------------------------------- +-- +-- Open Cores Mini UART +-- +----------------------------------------------------------------- + + component ACIA_6850 + port ( + clk : in Std_Logic; -- System Clock + rst : in Std_Logic; -- Reset input (active high) + cs : in Std_Logic; -- miniUART Chip Select + rw : in Std_Logic; -- Read / Not Write + irq : out Std_Logic; -- Interrupt + Addr : in Std_Logic; -- Register Select + DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In + DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out + RxC : in Std_Logic; -- Receive Baud Clock + TxC : in Std_Logic; -- Transmit Baud Clock + RxD : in Std_Logic; -- Receive Data + TxD : out Std_Logic; -- Transmit Data + DCD_n : in Std_Logic; -- Data Carrier Detect + CTS_n : in Std_Logic; -- Clear To Send + RTS_n : out Std_Logic -- Request To send + ); + end component; + +----------------------------------------------------------------- +-- +-- ACIA Clock divider +-- +----------------------------------------------------------------- + + component ACIA_Clock + generic ( + SYS_Clock_Frequency : integer := VGA_Clock_Frequency; + ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency + ); + port ( + clk : in Std_Logic; -- System Clock Input + ACIA_clk : out Std_logic -- ACIA Clock output + ); + end component; + + +---------------------------------------- +-- +-- PS/2 Keyboard +-- +---------------------------------------- + + component keyboard + generic( + KBD_Clock_Frequency : integer := CPU_Clock_Frequency + ); + port( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic; + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irq : out std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic + ); + end component; + +---------------------------------------- +-- +-- Video Display Unit. +-- +---------------------------------------- + component vdu8 + generic( + VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ + VGA_CLOCK_FREQUENCY : integer := VGA_Clock_Frequency; -- HZ + VGA_HOR_CHARS : integer := 80; -- CHARACTERS + VGA_VER_CHARS : integer := 25; -- CHARACTERS + VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS + VGA_LINES_PER_CHAR : integer := 16; -- LINES + VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS + VGA_HOR_SYNC : integer := 96; -- PIXELS + VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS + VGA_VER_BACK_PORCH : integer := 13; -- LINES + VGA_VER_SYNC : integer := 1; -- LINES + VGA_VER_FRONT_PORCH : integer := 36 -- LINES + ); + port( + -- control register interface + vdu_clk : in std_logic; -- CPU Clock - 12.5MHz + vdu_rst : in std_logic; + vdu_cs : in std_logic; + vdu_rw : in std_logic; + vdu_addr : in std_logic_vector(2 downto 0); + vdu_data_in : in std_logic_vector(7 downto 0); + vdu_data_out : out std_logic_vector(7 downto 0); + + -- vga port connections + vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz + vga_red_o : out std_logic; + vga_green_o : out std_logic; + vga_blue_o : out std_logic; + vga_hsync_o : out std_logic; + vga_vsync_o : out std_logic + ); + end component; + +begin + + ----------------------------------------------------------------- + -- + -- ChipsScope Pro cores + -- + ----------------------------------------------------------------- + +-- i_icon : icon +-- port map(control0 => chipscope_control); +-- +-- i_ila : ila +-- port map(control => chipscope_control, +-- clk => ila_clock, +-- trig0(15 downto 8) => cpu_data_in, +-- trig0(23 downto 16) => cpu_data_out, +-- trig0(39 downto 24) => cpu_addr, +-- trig0(0) => cpu_clk, +-- trig0(1) => cpu_vma, +-- trig0(2) => ram_bhenx, +-- trig0(3) => ram_blenx, +-- trig0(4) => ram_cenx, +-- trig0(5) => ram_oenx, +-- trig0(6) => ram_wenx, +-- trig0(7) => vdu_clk); + + ----------------------------------------------------------------- + -- + -- CPU09 CPU core + -- + ----------------------------------------------------------------- + + my_cpu : entity cpu09 port map ( + clk => cpu_clk, + rst => reset, + rw => cpu_rw, + vma => cpu_vma, + address => cpu_addr, + data_in => cpu_data_in, + data_out => cpu_data_out, + halt => cpu_halt, + hold => cpu_hold, + irq => cpu_irq, + nmi => cpu_nmi, + firq => cpu_firq + ); + + ---------------------------------------- + -- + -- Maisforth ROM (Xilinx Block RAM, 16k) + -- + ---------------------------------------- + + my_maisforth_rom_16k : entity maisforth_rom_16k port map ( + clk => cpu_clk, + rst => reset, + cs => rom_cs, + rw => '1', + addr => cpu_addr(13 downto 0), + rdata => rom_data_out, + wdata => cpu_data_out + ); + + ----------------------------------------------------------------------------- + -- + -- Internal RAM (Xilinx Block RAM, 4k) + -- + ----------------------------------------------------------------------------- + + my_user_ram0_2k : entity ram_2k port map ( + clk => cpu_clk, + rst => reset, + cs => user_ram0_cs, + rw => cpu_rw, + addr => cpu_addr(10 downto 0), + rdata => user_ram0_dout, + wdata => cpu_data_out + ); + + my_user_ram1_2k : entity ram_2k port map ( + clk => cpu_clk, + rst => reset, + cs => user_ram1_cs, + rw => cpu_rw, + addr => cpu_addr(10 downto 0), + rdata => user_ram1_dout, + wdata => cpu_data_out + ); + + ----------------------------------------------------------------- + -- + -- 6850 ACIA + -- + ----------------------------------------------------------------- + + my_uart : entity acia_6850 port map ( + clk => cpu_clk, + rst => reset, + cs => uart_cs, + rw => cpu_rw, + irq => uart_irq, + Addr => cpu_addr(0), + Datain => cpu_data_out, + DataOut => uart_data_out, + RxC => baudclk, + TxC => baudclk, + RxD => fpga_rxd, + TxD => fpga_txd, + DCD_n => dcd_n, + CTS_n => fpga_cts, + RTS_n => fpga_rts + ); + + +---------------------------------------- +-- +-- PS/2 Keyboard Interface +-- +---------------------------------------- + my_keyboard : keyboard + generic map ( + KBD_Clock_Frequency => CPU_Clock_frequency + ) + port map( + clk => cpu_clk, + rst => reset, + cs => keyboard_cs, + rw => cpu_rw, + addr => cpu_addr(0), + data_in => cpu_data_out(7 downto 0), + data_out => keyboard_data_out(7 downto 0), + irq => keyboard_irq, + kbd_clk => ps2_clk1, + kbd_data => ps2_data1 + ); + +---------------------------------------- +-- +-- Video Display Unit instantiation +-- +---------------------------------------- + my_vdu : vdu8 + generic map( + VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ + VGA_CLOCK_FREQUENCY => VGA_Clock_Frequency, -- HZ + VGA_HOR_CHARS => 80, -- CHARACTERS + VGA_VER_CHARS => 25, -- CHARACTERS + VGA_PIXELS_PER_CHAR => 8, -- PIXELS + VGA_LINES_PER_CHAR => 16, -- LINES + VGA_HOR_BACK_PORCH => 40, -- PIXELS + VGA_HOR_SYNC => 96, -- PIXELS + VGA_HOR_FRONT_PORCH => 24, -- PIXELS + VGA_VER_BACK_PORCH => 13, -- LINES + VGA_VER_SYNC => 1, -- LINES + VGA_VER_FRONT_PORCH => 36 -- LINES + ) + port map( + + -- Control Registers + vdu_clk => cpu_clk, -- 12.5 MHz System Clock in + vdu_rst => reset, + vdu_cs => vdu_cs,