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URL https://opencores.org/ocsvn/System09/System09/trunk

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    /System09
    from Rev 186 to Rev 187
    Reverse comparison

Rev 186 → Rev 187

/trunk/rtl/System09_Digilent_ZyboZ20/btn_debounce.vhd
0,0 → 1,155
----------------------------------------------------------------------------
-- btn_debounce.vhd -- Button Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals generated by external push
-- buttons. It is designed to independently debounce 5 Push button signals.
-- Debouncing is done by only registering a change in a button state if
-- it remains constant for 2^16 clock cycles.
--
-- Port Descriptions:
--
-- BTN_I - The input button signals
-- CLK - Behavior is optimized for a 100 MHz clock
-- BTN_O - The debounced button signals
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
 
entity btn_debounce is
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
end btn_debounce;
 
architecture Behavioral of btn_debounce is
 
constant CNTR_MAX : std_logic_vector(15 downto 0) := (others => '1');
 
signal btn0_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn1_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn2_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal btn3_cntr : std_logic_vector(15 downto 0) := (others => '0');
 
 
signal btn0_reg : std_logic := '0';
signal btn1_reg : std_logic := '0';
signal btn2_reg : std_logic := '0';
signal btn3_reg : std_logic := '0';
 
begin
 
btn0_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn0_cntr = CNTR_MAX) then
btn0_reg <= not(btn0_reg);
end if;
end if;
end process;
 
btn0_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn0_reg = '1') xor (BTN_I(0) = '1')) then
if (btn0_cntr = CNTR_MAX) then
btn0_cntr <= (others => '0');
else
btn0_cntr <= btn0_cntr + 1;
end if;
else
btn0_cntr <= (others => '0');
end if;
end if;
end process;
 
btn1_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn1_cntr = CNTR_MAX) then
btn1_reg <= not(btn1_reg);
end if;
end if;
end process;
 
btn1_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn1_reg = '1') xor (BTN_I(1) = '1')) then
if (btn1_cntr = CNTR_MAX) then
btn1_cntr <= (others => '0');
else
btn1_cntr <= btn1_cntr + 1;
end if;
else
btn1_cntr <= (others => '0');
end if;
end if;
end process;
 
btn2_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn2_cntr = CNTR_MAX) then
btn2_reg <= not(btn2_reg);
end if;
end if;
end process;
 
btn2_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn2_reg = '1') xor (BTN_I(2) = '1')) then
if (btn2_cntr = CNTR_MAX) then
btn2_cntr <= (others => '0');
else
btn2_cntr <= btn2_cntr + 1;
end if;
else
btn2_cntr <= (others => '0');
end if;
end if;
end process;
 
btn3_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn3_cntr = CNTR_MAX) then
btn3_reg <= not(btn3_reg);
end if;
end if;
end process;
 
btn3_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn3_reg = '1') xor (BTN_I(3) = '1')) then
if (btn3_cntr = CNTR_MAX) then
btn3_cntr <= (others => '0');
else
btn3_cntr <= btn3_cntr + 1;
end if;
else
btn3_cntr <= (others => '0');
end if;
end if;
end process;
 
 
 
BTN_O <= btn3_reg & btn2_reg & btn1_reg & btn0_reg;
 
end Behavioral;
 
/trunk/rtl/System09_Digilent_ZyboZ20/system09.gise
77,35 → 77,35
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341588" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341636" xil_pn:in_ck="4010317442951213546" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611341588">
<transform xil_pn:end_ts="1611362027" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611361980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1611341636" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611341636">
<transform xil_pn:end_ts="1611362027" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611362027">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611341645" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611341636">
<transform xil_pn:end_ts="1611362036" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611362027">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
136,11 → 136,9
<outfile xil_pn:name="system09.ngd"/>
<outfile xil_pn:name="system09_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611341679" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611341645">
<transform xil_pn:end_ts="1611362069" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611362036">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system09.pcf"/>
<outfile xil_pn:name="system09_map.map"/>
151,8 → 149,9
<outfile xil_pn:name="system09_summary.xml"/>
<outfile xil_pn:name="system09_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1611341715" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611341679">
<transform xil_pn:end_ts="1611362107" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611362069">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system09.ncd"/>
165,7 → 164,7
<outfile xil_pn:name="system09_pad.txt"/>
<outfile xil_pn:name="system09_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611341751" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611341715">
<transform xil_pn:end_ts="1611362141" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611362107">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
178,7 → 177,7
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1611341715" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611341702">
<transform xil_pn:end_ts="1611362107" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611362094">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/trunk/rtl/System09_Digilent_ZyboZ20/system09.prj
8,6 → 8,7
vhdl work "../VHDL/ACIA_Clock.vhd"
vhdl work "../VHDL/acia6850.vhd"
vhdl work "common.vhd"
vhdl work "btn_debounce.vhd"
vhdl work "../Spartan3/ram32k_b16.vhd"
vhdl work "../Spartan3/ram16k_b16.vhd"
vhdl work "system09.vhd"
/trunk/rtl/System09_Digilent_ZyboZ20/system09.ucf
10,10 → 10,10
##Clock signal
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
NET "sysclk" LOC = "K17";
NET "sysclk" IOSTANDARD = LVCMOS33;
NET "sysclk" TNM_NET="sysclk";
TIMESPEC "TS_clk"=PERIOD "sysclk" 10 ns HIGH 50 %;
NET "CLKA" LOC = "K17";
NET "CLKA" IOSTANDARD = LVCMOS33;
NET "CLKA" TNM_NET="CLKA";
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
 
##Switches
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
20,17 → 20,28
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
NET "sw[0]" LOC = "G15";
NET "sw[0]" IOSTANDARD = LVCMOS33;
NET "sw[1]" LOC = "P15";
NET "sw[1]" IOSTANDARD = LVCMOS33;
NET "sw[2]" LOC = "W13";
NET "sw[2]" IOSTANDARD = LVCMOS33;
NET "sw[3]" LOC = "T16";
NET "sw[3]" IOSTANDARD = LVCMOS33;
 
 
##Buttons
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { RESET_N }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { NMI_N }]; #IO_L24N_T3_34 Sch=btn[1]
NET "RESET_N" LOC = "K18";
NET "RESET_N" IOSTANDARD = LVCMOS33;
NET "NMI_N" LOC = "P16";
NET "NMI_N" IOSTANDARD = LVCMOS33;
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
NET "btn[0]" LOC = "K18";
NET "btn[0]" IOSTANDARD = LVCMOS33;
NET "btn[1]" LOC = "P16";
NET "btn[1]" IOSTANDARD = LVCMOS33;
NET "btn[2]" LOC = "K19";
NET "btn[2]" IOSTANDARD = LVCMOS33;
NET "btn[3]" LOC = "Y16";
NET "btn[3]" IOSTANDARD = LVCMOS33;
 
##LEDs
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
37,8 → 48,24
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
NET "led[0]" LOC = "M14";
NET "led[0]" IOSTANDARD = LVCMOS33;
NET "led[0]" DRIVE = 12;
NET "led[0]" SLEW = SLOW;
NET "led[1]" LOC = "M15";
NET "led[1]" IOSTANDARD = LVCMOS33;
NET "led[1]" DRIVE = 12;
NET "led[1]" SLEW = SLOW;
NET "led[2]" LOC = "G14";
NET "led[2]" IOSTANDARD = LVCMOS33;
NET "led[2]" DRIVE = 12;
NET "led[2]" SLEW = SLOW;
NET "led[3]" LOC = "D18";
NET "led[3]" IOSTANDARD = LVCMOS33;
NET "led[3]" DRIVE = 12;
NET "led[3]" SLEW = SLOW;
 
 
 
##RGB LED 5 (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
174,6 → 201,12
# 2 output RTS je<1> input W16
# 3 output TXD je<2> input J15
# 4 input RXD je<3> output H15
NET "RS232_RTS" LOC = "V12";
NET "RS232_RTS" IOSTANDARD = LVCMOS33;
NET "RS232_CTS" LOC = "W16";
NET "RS232_CTS" IOSTANDARD = LVCMOS33;
NET "RS232_CTS" DRIVE = 12;
NET "RS232_CTS" SLEW = SLOW;
NET "RS232_RXD" LOC = "J15";
NET "RS232_RXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "H15";
/trunk/rtl/System09_Digilent_ZyboZ20/system09.vhd
5,19 → 5,41
-- www.OpenCores.Org - February 2007
-- This core adheres to the GNU public license
--
-- File name : System09_Xess_XSA-3S1000.vhd
-- File name : system09.vhd
--
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Xilinx XC3S1000 Spartan 3 FPGA.
-- Implemented With XESS XSA-3S1000 FPGA board.
-- *** Note ***
-- This configuration can run Flex9 however it only has
-- 32k bytes of user memory and the VDU is monochrome
-- The design needs to be updated to use the SDRAM on
-- the XSA-3S1000 board.
-- This configuration also lacks a DAT so cannot use
-- the RAM Disk features of SYS09BUG.
-- Designed with Digilent Zybo Z20.
-- ==========================================================================
-- Setup/Buttons
-- RS232 - connect a RS-232 Pmod to JE (upper row)
-- Configure terminal for 57600 baud 8-N-1, hardware handshake
--
-- Slide Switches - selects the nibble to display on the 4 LEDs
-- 0000 - CPU Address 3 to 0
-- 0001 - CPU Address 7 to 4
-- 0010 - CPU Address 11 to 8
-- 0011 - CPU Address 15 to 12
-- 0100 - CPU Data 3 to 0
-- 0101 - CPU Data 7 to 4
--
-- Push buttons
-- BTN3 BTN2 BTN1 BTN0
-- (unused) Single NMI RESET
-- Step
--
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
--
-- Memory Map :
--
-- $0000 - User program RAM (32K Bytes)
-- $8000 - User program RAM (16K Bytes)
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E050 - Timer
-- $E060 - Bus trap
-- $F000 - Sys09Bug monitor Program (4K Bytes)
-- ==========================================================================
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
24,97 → 46,22
-- ieee.numeric_std
-- unisim.vcomponents
--
-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
-- cpu09 (cpu09.vhd) CPU core
-- ACIA_6850 (acia6850.vhd) ACIA / UART
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
-- Uses : mon_rom (sys09swt.vhd) SWTPc S-Bug 1.7 Monitor ROM
-- cpu09 (cpu09.vhd) CPU core
-- ACIA_6850 (acia6850.vhd) ACIA / UART
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
-- timer (timer.vhd) Interrupt timer
-- trap (trap.vhd) Bus condition trap logic
-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system
-- flex_ram (flex9ram.vhd) Flex operating system
-- ram_16K (ram16k_b16.vhd) 32 KBytes of Block RAM
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
--
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Memory Map :
--
-- $0000 - User program RAM (32K Bytes)
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Reserced for Parallel I/O (B5-X300)
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $F000 - Sys09Bug monitor Program (4K Bytes)
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 2.0 - 2 September 2004 - John Kent
-- ported to Digilent Xilinx Spartan3 starter board
-- removed Compact Flash and Trap Logic.
-- Replaced SBUG with KBug9s
--
-- Version 3.0 - 29th August 2006 - John Kent
-- Adapted to XSA-3S1000 board.
-- Removed DAT and miniUART.
-- Used 32KBytes of Block RAM.
--
-- Version 3.1 - 15th January 2007 - John Kent
-- Modified vdu8 interface
-- Added a clock divider
--
-- Version 3.2 - 25th February 2007 - John Kent
-- reinstated ACIA_6850 and ACIA_Clock
-- Updated VDU8 & Keyboard with generic parameters
-- Defined Constants for clock speed calculations
--
-- Version 3.3 - 1st July 2007 - John Kent
-- Made VDU mono to save on one RAMB16
-- Used distributed memory for Key Map ROM to save one RAMB16
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
-- Added timer and trap logic
-- Added IDE Interface for Compact Flash
-- Replaced KBug9s and stack with Sys09Bug.
--
-- Version 4.0 - 1st February 2008 - John kent
-- Replaced Block RAM with SDRAM Interface
-- Modified Hold timing for SDRAM
-- Added CF and Ethernet interface
-- via the 16 bit peripheral bus at $E100
--
-- Version 0.1 - Jan 20, 2021
-- Copied from the System09_Xess-XSA3S1000 vhdl
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
128,30 → 75,20
 
entity system09 is
port(
sysclk : in Std_Logic; -- 125MHz Clock input
RESET_N : in Std_logic; -- Master Reset input (active low)
NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
CLKA : in Std_Logic; -- 125 MHz Clock input
 
-- RS232 Port
--RS232_CTS : in std_logic;
--RS232_RTS : out std_logic;
RS232_RXD : in Std_Logic; -- RS-232 data in
RS232_TXD : out Std_Logic -- RS-232 data out
RS232_RTS : out std_logic;
RS232_CTS : in std_logic;
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
-- CPU Debug Interface signals
-- cpu_reset_o : out Std_Logic;
-- cpu_clk_o : out Std_Logic;
-- cpu_rw_o : out std_logic;
-- cpu_vma_o : out std_logic;
-- cpu_halt_o : out std_logic;
-- cpu_hold_o : out std_logic;
-- cpu_firq_o : out std_logic;
-- cpu_irq_o : out std_logic;
-- cpu_nmi_o : out std_logic;
-- cpu_addr_o : out std_logic_vector(15 downto 0);
-- cpu_data_in_o : out std_logic_vector(7 downto 0);
-- cpu_data_out_o : out std_logic_vector(7 downto 0);
-- slide switches
sw : in std_logic_vector(3 downto 0);
-- push buttons [Unused, Single-Step, NMI, RESET]
btn : in std_logic_vector(3 downto 0);
-- Status 4 LEDs
led : out std_logic_vector(3 downto 0)
);
end system09;
 
163,7 → 100,9
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
172,7 → 111,11
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
signal pbtn : std_logic_vector(3 downto 0);
signal NMI_N : std_logic;
signal RESET_N : std_logic;
signal SINGLE_STEP : std_logic;
-- BOOT ROM
signal rom_cs : Std_logic;
signal rom_data_out : Std_Logic_Vector(7 downto 0);
228,13 → 171,19
signal trap_irq : std_logic;
 
signal rst_i : std_logic; -- internal reset signal
signal clk_i : std_logic; -- internal master clock signal
 
signal rs232_cts : Std_Logic;
signal rs232_rts : Std_Logic;
signal clk_i : std_logic; -- internal master clock signal
signal CountL : std_logic_vector(23 downto 0);
signal clk_count : natural range 0 to CPU_CLK_DIV;
signal Clk25 : std_logic;
 
 
component btn_debounce
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
end component;
 
 
-----------------------------------------------------------------
--
436,12 → 385,10
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
 
--
-- Clock buffer
--
----------------------------------------
 
component BUFG
Port (
450,9 → 397,53
);
end component;
 
begin
begin
 
clk_i <= sysclk;
--
-- pushbutton debounce
--
my_singlestep: btn_debounce
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
RESET_N <= pbtn(0); -- Right PB
NMI_N <= pbtn(1); -- Center PB
SINGLE_STEP <= pbtn(2); -- Left PB
--
-- Generate CPU & Pixel Clock from Memory Clock
--
NORMAL: if CLOCK_MODE = 0 generate
my_prescaler : process( clk_i, clk_count )
begin
if rising_edge( clk_i ) then
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
if clk_count = 0 then
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
end if;
end if;
end process;
end generate;
SS: if CLOCK_MODE = 1 generate
clk25 <= SINGLE_STEP;
end generate;
 
--
-- Reset button and reset timer
--
my_switch_assignments : process( rst_i, RESET_N)
begin
rst_i <= RESET_N;
cpu_reset <= rst_i;
end process;
 
clk_i <= CLKA;
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
529,16 → 520,17
irq => acia_irq,
RxC => acia_clk,
TxC => acia_clk,
RxD => rxd,
TxD => txd,
RxD => RS232_RXD,
TxD => RS232_TXD,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
CTS_n => RS232_CTS,
RTS_n => RS232_RTS
);
 
dcd_n <= '0';
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_CLK_FREQ => SYS_CLK_FREQ,
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
749,43 → 741,38
end process;
 
--
-- Generate CPU & Pixel Clock from Memory Clock
-- Flash 7 segment LEDS
--
my_prescaler : process( clk_i, clk_count )
my_led_flasher: process( clk_i, rst_i, CountL )
begin
if rising_edge( clk_i ) then
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
if clk_count = 0 then
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
end if;
if rst_i = '1' then
CountL <= "000000000000000000000000";
elsif rising_edge(clk_i) then
CountL <= CountL + 1;
end if;
end process;
 
--
-- Reset button and reset timer
--
my_switch_assignments : process( rst_i, RESET_N)
begin
rst_i <= RESET_N;
cpu_reset <= rst_i;
--S(7 downto 0) <= CountL(23 downto 16);
end process;
 
--
-- RS232 signals:
--
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
begin
rxd <= RS232_RXD;
cts_n <= RS232_CTS;
dcd_n <= '0';
RS232_TXD <= txd;
RS232_RTS <= rts_n;
 
 
 
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
begin
case sw is
when "0000" =>
led(3 downto 0) <= cpu_addr(3 downto 0);
when "0001" =>
led(3 downto 0) <= cpu_addr(7 downto 4);
when "0010" =>
led(3 downto 0) <= cpu_addr(11 downto 8);
when "0011" =>
led(3 downto 0) <= cpu_addr(15 downto 12);
when "0100" =>
led(3 downto 0) <= cpu_data_in(3 downto 0);
when "0101" =>
led(3 downto 0) <= cpu_data_in(7 downto 4);
when others => led(3 downto 0) <= (others => '0');
end case;
end process;
 
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
/trunk/rtl/System09_Digilent_ZyboZ20/system09.xise
57,19 → 57,23
</file>
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="system09.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="btn_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
</files>
 
<properties>

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