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Rev 169 → Rev 170

/System09/trunk/rtl/System09_Digilent_Atlys/system09.prj
8,4 → 8,5
vhdl work "../VHDL/ACIA_Clock.vhd"
vhdl work "../VHDL/acia6850.vhd"
vhdl work "common.vhd"
vhdl work "../Spartan3/ram32k_b16.vhd"
vhdl work "system09.vhd"
/System09/trunk/rtl/System09_Digilent_Atlys/system09.ucf
6,7 → 6,7
#
# Clocks
#
# clock pin for Atlys rev C board
# clock pin for Atlys rev C board - 100 MHz
NET "CLKA" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
 
#
26,12 → 26,12
NET "S<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
NET "S<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
NET "S<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
 
#NET "S<4>" LOC = "T3";
#
# RS232 PORT
#
# NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
# NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
 
# Using PMOD connection
# RS-232 PMod Pin Function PMOD PinLoc
39,8 → 39,8
# 2 RTS JA2 R3
# 3 TXD JA3 P6
# 4 RXD JA4 N5
NET "RS232_RXD" LOC = "N5"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
NET "RS232_TXD" LOC = "P6"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
# NET "RS232_RXD" LOC = "N5"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
# NET "RS232_TXD" LOC = "P6"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
 
#
# PS/2 Keyboard via USB HID Host port
/System09/trunk/rtl/System09_Digilent_Atlys/system09.vhd
165,19 → 165,10
-- constants
-----------------------------------------------------------------------------
 
-- SDRAM
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations
constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
constant DATA_WIDTH : natural := 16; -- host & SDRAM data width
constant NROWS : natural := 8192; -- number of rows in SDRAM array
constant NCOLS : natural := 512; -- number of columns in SDRAM array
constant HADDR_WIDTH : natural := 24; -- host-side address width
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
 
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz)
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
constant BAUD_RATE : integer := 57600; -- Baud Rate
211,12 → 202,8
signal CTS_n : Std_Logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_cs : std_logic;
signal ram_data_out : std_logic_vector(7 downto 0);
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
signal ram_hold : std_logic; -- hold off slow accesses
signal ram_release : std_logic; -- Release ram hold
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
246,49 → 233,12
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- Peripheral Bus port
signal pb_data_out : std_logic_vector(7 downto 0);
signal pb_cs : std_logic; -- peripheral bus chip select
signal pb_wru : std_logic; -- upper byte write strobe
signal pb_wrl : std_logic; -- lower byte write strobe
signal pb_rdu : std_logic; -- upper byte read strobe
signal pb_rdl : std_logic; -- lower byte read strobe
signal pb_hold : std_logic; -- hold peripheral bus access
signal pb_release : std_logic; -- release hold of peripheral bus
signal pb_count : std_logic_vector(3 downto 0); -- hold counter
signal pb_hold_state : hold_state_type;
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
 
signal rst_i : std_logic; -- internal reset signal
signal clk_i : std_logic; -- internal master clock signal
 
-- signals that go through the SDRAM host-side interface
signal opBegun : std_logic; -- SDRAM operation started indicator
signal earlyBegun : std_logic; -- SDRAM operation started indicator
signal ramDone : std_logic; -- SDRAM operation complete indicator
signal rdDone : std_logic; -- SDRAM read operation complete indicator
signal wrDone : std_logic; -- SDRAM write operation complete indicator
signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus
signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
signal hRd : std_logic; -- host-side read control signal
signal hWr : std_logic; -- host-side write control signal
signal hUds : std_logic; -- host-side upper data strobe
signal hLds : std_logic; -- host-side lower data strobe
signal rdPending : std_logic; -- read operation pending in SDRAM pipeline
type ram_type is (ram_state_0,
ram_state_rd1, ram_state_rd2,
ram_state_wr1,
ram_state_3 );
signal ram_state : ram_type;
 
signal flash_ce_n : std_logic;
signal rs232_cts : Std_Logic;
signal rs232_rts : Std_Logic;
 
signal rs232_cts : Std_Logic;
signal rs232_rts : Std_Logic;
-- signal BaudCount : std_logic_vector(5 downto 0);
 
signal CountL : std_logic_vector(23 downto 0);
signal clk_count : natural range 0 to CPU_CLK_DIV;
signal Clk25 : std_logic;
353,7 → 303,27
data_in : in std_logic_vector (7 downto 0)
);
end component;
 
----------------------------------------
--
-- 32KBytes Block RAM 0000
-- $0000 - $7FFF
--
----------------------------------------
 
component ram_32k
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (14 downto 0);
data_out : out std_logic_vector (7 downto 0);
data_in : in std_logic_vector (7 downto 0)
);
end component;
 
 
-----------------------------------------------------------------
--
-- 6850 Compatible ACIA / UART
510,7 → 480,18
addr => cpu_addr(12 downto 0),
data_out => flex_data_out,
data_in => cpu_data_out
);
);
my_32k : ram_32k
port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ram_cs,
rw => cpu_rw,
addr => cpu_addr(14 downto 0),
data_out => ram_data_out,
data_in => cpu_data_out
);
 
my_acia : acia6850
port map (
605,7 → 586,6
rom_data_out,
flex_data_out,
acia_data_out,
pb_data_out,
timer_data_out,
trap_data_out,
ram_data_out
618,7 → 598,6
acia_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
pb_cs <= '0';
ram_cs <= '0';
 
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
703,6 → 682,13
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
cpu_data_in <= flex_data_out;
flex_cs <= cpu_vma;
 
--
-- 32k RAM $00000 - $07FFF
--
elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
 
--
-- Everything else is RAM
718,19 → 704,16
-- Interrupts and other bus control signals
--
interrupts : process( SW3_N,
pb_cs, pb_hold, pb_release, ram_hold,
acia_irq,
trap_irq,
timer_irq
)
begin
pb_hold <= pb_cs and (not pb_release);
cpu_irq <= acia_irq;
cpu_nmi <= trap_irq or not( SW3_N );
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= pb_hold or ram_hold;
FLASH_CE_N <= '1';
cpu_hold <= '0'; -- pb_hold or ram_hold;
end process;
 
--
786,43 → 769,15
RS232_RTS <= rts_n;
end process;
 
--
-- CPU read data request on rising CPU clock edge
--
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw)
begin
if hRd = '1' then
ram_rd_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
ram_rd_req <= '1';
end if;
end if;
end process;
 
--
-- CPU write data to RAM valid on rising CPU clock edge
--
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
begin
if hWr = '1' then
ram_wr_req <= '0';
elsif rising_edge(cpu_clk) then
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
ram_wr_req <= '1';
end if;
end if;
end process;
 
status_leds : process( rst_i, cpu_reset)
begin
S(0) <= cpu_reset;
S(1) <= countL(23);
S(2) <= RS232_RXD;
S(3) <= txd;
S(4) <= Clk25;
S(5) <= '0';
S(6) <= '0';
S(0) <= cpu_addr(0);
S(1) <= cpu_addr(1);
S(2) <= cpu_addr(2);
S(3) <= cpu_addr(3);
S(4) <= cpu_addr(4);
S(5) <= cpu_addr(5);
S(6) <= cpu_rw;
S(7) <= '0';
--S(7 downto 4) <= "0000";
end process;
/System09/trunk/rtl/System09_Digilent_Atlys/system09.xise
51,10 → 51,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../Spartan3/ram2k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../VHDL/bit_funcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
64,6 → 60,10
</file>
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
</files>

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