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Rev 56 → Rev 57
/branches/mkfiles_rev1/rtl/System09_Memec_XC2V1000/my_system09.ise
Cannot display: file marked as a binary type.
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/branches/mkfiles_rev1/rtl/System09_Memec_XC2V1000/System09_Memec_XC2V1000.vhd
152,7 → 152,7
----------------------------------------------------------------------------- |
-- constants |
----------------------------------------------------------------------------- |
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock |
constant SYS_Clock_Frequency : integer := 100000000; -- FPGA System Clock |
constant VGA_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock |
constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock |
constant BAUD_Rate : integer := 57600; -- Baud Rate |
232,7 → 232,8
|
-- System Clock Prescaler |
signal clk_count : std_logic; |
|
signal Clk50 : std_logic; |
|
----------------------------------------------------------------- |
-- |
-- CPU09 CPU core |
623,6 → 624,13
o => cpu_clk |
); |
|
clk50_clock : process( sys_clk, Clk50 ) |
begin |
if sys_clk'event and sys_clk='1' then |
Clk50 <= not Clk50; |
end if; |
end process; |
|
-- |
-- Clock divider |
-- Assumes 50 MHz system clock |
629,9 → 637,9
-- 25MHz pixel clock |
-- 25MHz CPU clock |
-- |
sys09_clock : process( sys_clk, clk_count ) |
sys09_clock : process( Clk50, clk_count ) |
begin |
if sys_clk'event and sys_clk='1' then |
if Clk50'event and CLk50='1' then |
clk_count <= not clk_count; |
end if; |
end process; |