URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/System09_Digilent_ZyboZ20
- from Rev 187 to Rev 193
- ↔ Reverse comparison
Rev 187 → Rev 193
/system09.gise
77,35 → 77,35
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611361980" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611362027" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611361980"> |
<transform xil_pn:end_ts="1611953252" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611953203"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1611362027" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611362027"> |
<transform xil_pn:end_ts="1611953252" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611953252"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1611362036" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611362027"> |
<transform xil_pn:end_ts="1611953261" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611953252"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
136,9 → 136,11
<outfile xil_pn:name="system09.ngd"/> |
<outfile xil_pn:name="system09_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611362069" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611362036"> |
<transform xil_pn:end_ts="1611953297" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611953261"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="system09.pcf"/> |
<outfile xil_pn:name="system09_map.map"/> |
149,7 → 151,7
<outfile xil_pn:name="system09_summary.xml"/> |
<outfile xil_pn:name="system09_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611362107" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611362069"> |
<transform xil_pn:end_ts="1611953337" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611953297"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
164,7 → 166,7
<outfile xil_pn:name="system09_pad.txt"/> |
<outfile xil_pn:name="system09_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1611362141" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611362107"> |
<transform xil_pn:end_ts="1611953373" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611953337"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
177,7 → 179,7
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1611362107" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611362094"> |
<transform xil_pn:end_ts="1611953337" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611953323"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
191,6 → 193,7
<status xil_pn:value="OutOfDateForced"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="InputRemoved"/> |
</transform> |
</transforms> |
|
/system09.vhd
77,9 → 77,9
port( |
CLKA : in Std_Logic; -- 125 MHz Clock input |
|
-- RS232 Port |
RS232_RTS : out std_logic; |
RS232_CTS : in std_logic; |
-- RS232 Port - via Pmod RS232 |
RS232_CTS : in Std_Logic; |
RS232_RTS : out Std_Logic; |
RS232_RXD : in Std_Logic; |
RS232_TXD : out Std_Logic; |
|
112,8 → 112,8
-- Signals |
----------------------------------------------------------------------------- |
signal pbtn : std_logic_vector(3 downto 0); |
signal NMI_N : std_logic; |
signal RESET_N : std_logic; |
signal NMI : std_logic; |
signal RESET : std_logic; |
signal SINGLE_STEP : std_logic; |
|
-- BOOT ROM |
129,8 → 129,8
signal acia_cs : Std_Logic; |
signal acia_irq : Std_Logic; |
signal acia_clk : Std_Logic; |
signal rxd : Std_Logic; |
signal txd : Std_Logic; |
signal RXD : Std_Logic; |
signal TXD : Std_Logic; |
signal DCD_n : Std_Logic; |
signal RTS_n : Std_Logic; |
signal CTS_n : Std_Logic; |
405,8 → 405,8
my_singlestep: btn_debounce |
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn); |
|
RESET_N <= pbtn(0); -- Right PB |
NMI_N <= pbtn(1); -- Center PB |
RESET <= pbtn(0); -- Right PB |
NMI <= pbtn(1); -- Center PB |
SINGLE_STEP <= pbtn(2); -- Left PB |
|
-- |
436,9 → 436,9
-- |
-- Reset button and reset timer |
-- |
my_switch_assignments : process( rst_i, RESET_N) |
my_switch_assignments : process( rst_i, RESET) |
begin |
rst_i <= RESET_N; |
rst_i <= RESET; |
cpu_reset <= rst_i; |
end process; |
|
520,13 → 520,24
irq => acia_irq, |
RxC => acia_clk, |
TxC => acia_clk, |
RxD => RS232_RXD, |
TxD => RS232_TXD, |
DCD_n => dcd_n, |
CTS_n => RS232_CTS, |
RTS_n => RS232_RTS |
); |
dcd_n <= '0'; |
RxD => RXD, |
TxD => TXD, |
DCD_n => DCD_n, |
CTS_n => CTS_n, |
RTS_n => RTS_n |
); |
|
-- |
-- RS232 signals: |
-- |
my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n ) |
begin |
RXD <= RS232_RXD; |
CTS_n <= RS232_CTS; |
DCD_n <= '0'; |
RS232_TXD <= TXD; |
RS232_RTS <= RTS_n; |
end process; |
|
my_ACIA_Clock : ACIA_Clock |
generic map( |
534,7 → 545,7
ACIA_CLK_FREQ => ACIA_CLK_FREQ |
) |
port map( |
clk => Clk_i, |
clk => clk_i, |
acia_clk => acia_clk |
); |
|
692,29 → 703,29
when others => |
null; |
end case; |
|
-- |
-- Flex RAM $0C000 - $0DFFF |
-- |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF |
cpu_data_in <= flex_data_out; |
flex_cs <= cpu_vma; |
|
-- |
-- 32k RAM $00000 - $07FFF |
-- Block RAM (32k) $00000 - $07FFF |
-- |
elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF |
elsif dat_addr(7 downto 3) = "00000" then -- $00000 - $07FFF |
cpu_data_in <= ram1_data_out; |
ram1_cs <= cpu_vma; |
|
-- |
-- 16k RAM $08000 - $0BFFF |
-- Block RAM (16k) $08000 - $0BFFF |
-- |
elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF |
elsif dat_addr(7 downto 2) = "000010" then -- $08000 - $0BFFF |
cpu_data_in <= ram2_data_out; |
ram2_cs <= cpu_vma; |
|
-- |
-- Flex RAM (8k) $0C000 - $0DFFF |
-- |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF |
cpu_data_in <= flex_data_out; |
flex_cs <= cpu_vma; |
|
-- |
-- Everything else is RAM |
-- |
else |
727,7 → 738,7
-- |
-- Interrupts and other bus control signals |
-- |
interrupts : process( NMI_N, |
interrupts : process( NMI, |
acia_irq, |
trap_irq, |
timer_irq |
734,7 → 745,7
) |
begin |
cpu_irq <= acia_irq; |
cpu_nmi <= trap_irq or not( NMI_N ); |
cpu_nmi <= trap_irq or NMI; |
cpu_firq <= timer_irq; |
cpu_halt <= '0'; |
cpu_hold <= '0'; -- pb_hold or ram_hold; |
753,10 → 764,7
--S(7 downto 0) <= CountL(23 downto 16); |
end process; |
|
|
|
|
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw) |
status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw) |
begin |
case sw is |
when "0000" => |