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  • This comparison shows the changes necessary to convert path 
    /System09/trunk/rtl/System09_Digilent_ZyboZ20
    from Rev 193 to Rev 196
    ↔ Reverse comparison
  •

Rev 193 → Rev 196

/system09.gise
77,35 → 77,35
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4547354422454731594" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5792613228111658103" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2491246652047045050" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8962985228163541850" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1611953203" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970197" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="581572070174917633" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611953252" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611953203">
<transform xil_pn:end_ts="1611970247" xil_pn:in_ck="8320588413340917314" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="6281697641096356723" xil_pn:start_ts="1611970197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
123,11 → 123,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1611953252" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611953252">
<transform xil_pn:end_ts="1611970247" xil_pn:in_ck="6003168217582152378" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3128816144678396997" xil_pn:start_ts="1611970247">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1611953261" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611953252">
<transform xil_pn:end_ts="1611970256" xil_pn:in_ck="-2676906326711859666" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2224943507431214821" xil_pn:start_ts="1611970247">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
136,11 → 136,9
<outfile xil_pn:name="system09.ngd"/>
<outfile xil_pn:name="system09_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611953297" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611953261">
<transform xil_pn:end_ts="1611970295" xil_pn:in_ck="-1009016811758874705" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="7139365205243936037" xil_pn:start_ts="1611970256">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system09.pcf"/>
<outfile xil_pn:name="system09_map.map"/>
151,7 → 149,7
<outfile xil_pn:name="system09_summary.xml"/>
<outfile xil_pn:name="system09_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1611953337" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611953297">
<transform xil_pn:end_ts="1611970334" xil_pn:in_ck="-7782462315172532792" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="378965794422880756" xil_pn:start_ts="1611970295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
166,7 → 164,7
<outfile xil_pn:name="system09_pad.txt"/>
<outfile xil_pn:name="system09_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1611953373" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611953337">
<transform xil_pn:end_ts="1611970369" xil_pn:in_ck="6003168217582144753" xil_pn:name="TRANEXT_bitFile_zynq" xil_pn:prop_ck="-8808622799194500101" xil_pn:start_ts="1611970334">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
179,7 → 177,7
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1611953337" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611953323">
<transform xil_pn:end_ts="1611970334" xil_pn:in_ck="190496098961729835" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-1758799009971969898" xil_pn:start_ts="1611970320">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/system09.ucf
201,12 → 201,12
# 2 output RTS je<1> input W16
# 3 output TXD je<2> input J15
# 4 input RXD je<3> output H15
NET "RS232_RTS" LOC = "V12";
NET "RS232_RTS" IOSTANDARD = LVCMOS33;
NET "RS232_CTS" LOC = "W16";
NET "RS232_CTS" IOSTANDARD = LVCMOS33;
NET "RS232_CTS" DRIVE = 12;
NET "RS232_CTS" SLEW = SLOW;
# NET "RS232_RTS" LOC = "V12";
# NET "RS232_RTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" LOC = "W16";
# NET "RS232_CTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" DRIVE = 12;
# NET "RS232_CTS" SLEW = SLOW;
NET "RS232_RXD" LOC = "J15";
NET "RS232_RXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "H15";
/system09.vhd
78,8 → 78,8
CLKA : in Std_Logic; -- 125 MHz Clock input
 
-- RS232 Port - via Pmod RS232
RS232_CTS : in Std_Logic;
RS232_RTS : out Std_Logic;
-- RS232_CTS : in Std_Logic;
-- RS232_RTS : out Std_Logic;
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
173,7 → 173,7
signal rst_i : std_logic; -- internal reset signal
signal clk_i : std_logic; -- internal master clock signal
signal CountL : std_logic_vector(23 downto 0);
signal CountL : std_logic_vector(25 downto 0);
signal clk_count : natural range 0 to CPU_CLK_DIV;
signal Clk25 : std_logic;
 
407,31 → 407,26
RESET <= pbtn(0); -- Right PB
NMI <= pbtn(1); -- Center PB
SINGLE_STEP <= pbtn(2); -- Left PB
--
-- Generate CPU & Pixel Clock from Memory Clock
--
NORMAL: if CLOCK_MODE = 0 generate
my_prescaler : process( clk_i, clk_count )
begin
if rising_edge( clk_i ) then
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
if clk_count = 0 then
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
end if;
 
my_prescaler : process( clk_i, clk_count )
begin
if rising_edge( clk_i ) then
if clk_count = 0 then
clk_count <= CPU_CLK_DIV-1;
else
clk_count <= clk_count - 1;
end if;
end process;
end generate;
SS: if CLOCK_MODE = 1 generate
clk25 <= SINGLE_STEP;
end generate;
if clk_count = 0 then
clk25 <= '0';
elsif clk_count = (CPU_CLK_DIV/2) then
clk25 <= '1';
end if;
end if;
end process;
 
--
-- Reset button and reset timer
530,13 → 525,14
--
-- RS232 signals:
--
my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n )
my_acia_assignments : process( RS232_RXD, --RS232_CTS,
TXD, RTS_n )
begin
RXD <= RS232_RXD;
CTS_n <= RS232_CTS;
CTS_n <= '0'; -- not RS232_CTS;
DCD_n <= '0';
RS232_TXD <= TXD;
RS232_RTS <= RTS_n;
-- RS232_RTS <= not RTS_n;
end process;
my_ACIA_Clock : ACIA_Clock
757,7 → 753,7
my_led_flasher: process( clk_i, rst_i, CountL )
begin
if rst_i = '1' then
CountL <= "000000000000000000000000";
CountL <= "00000000000000000000000000";
elsif rising_edge(clk_i) then
CountL <= CountL + 1;
end if;
767,18 → 763,23
status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
begin
case sw is
when "0000" =>
when "1000" =>
led(3 downto 0) <= cpu_addr(3 downto 0);
when "0001" =>
when "1001" =>
led(3 downto 0) <= cpu_addr(7 downto 4);
when "0010" =>
when "1010" =>
led(3 downto 0) <= cpu_addr(11 downto 8);
when "0011" =>
when "1011" =>
led(3 downto 0) <= cpu_addr(15 downto 12);
when "0100" =>
when "1100" =>
led(3 downto 0) <= cpu_data_in(3 downto 0);
when "0101" =>
led(3 downto 0) <= cpu_data_in(7 downto 4);
when "1101" =>
led(3 downto 0) <= cpu_data_in(7 downto 4);
when "0000" =>
led(3) <= '0';
led(2) <= CountL(24);
led(1) <= cpu_reset;
led(0) <= NMI;
when others => led(3 downto 0) <= (others => '0');
end case;
end process;

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