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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path
    /System09/trunk/rtl/System09_Digilent_ZyboZ20
    from Rev 198 to Rev 199
    Reverse comparison

Rev 198 → Rev 199

/system09.ucf
219,18 → 219,18
 
# PmodUSBUART Zybo Pmod Port JE
# Pin Dir Function PMOD Dir Function PinLoc
# 1 output RTS je<0> input RTS
# 1 output RTS je<0> input CTS V12
# 2 input RXD je<1> output TXD W16
# 3 output TXD je<2> input RXD J15
# 4 input CTS je<3> output CTS
# 4 input CTS je<3> output RTS H15
# 5 GND
# 6 SYS3V3 (make sure Pmod jumper JP1 is LCL-VCC not VCC-SYS to avoid driving 3.3V onto Zybo board)
# NET "RS232_RTS" LOC = "V12";
# NET "RS232_RTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" LOC = "W16";
# NET "RS232_CTS" IOSTANDARD = LVCMOS33;
# NET "RS232_CTS" DRIVE = 12;
# NET "RS232_CTS" SLEW = SLOW;
NET "RS232_RTS" LOC = "H15";
NET "RS232_RTS" IOSTANDARD = LVCMOS33;
NET "RS232_RTS" DRIVE = 12;
NET "RS232_RTS" SLEW = SLOW;
NET "RS232_CTS" LOC = "V12";
NET "RS232_CTS" IOSTANDARD = LVCMOS33;
NET "RS232_RXD" LOC = "J15";
NET "RS232_RXD" IOSTANDARD = LVCMOS33;
NET "RS232_TXD" LOC = "W16";
/system09.vhd
78,8 → 78,8
CLKA : in Std_Logic; -- 125 MHz Clock input
 
-- RS232 Port - via Pmod RS232
-- RS232_CTS : in Std_Logic;
-- RS232_RTS : out Std_Logic;
RS232_CTS : in Std_Logic;
RS232_RTS : out Std_Logic;
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
525,14 → 525,14
--
-- RS232 signals:
--
my_acia_assignments : process( RS232_RXD, --RS232_CTS,
my_acia_assignments : process( RS232_RXD, RS232_CTS,
TXD, RTS_n )
begin
RXD <= RS232_RXD;
CTS_n <= '0'; -- not RS232_CTS;
CTS_n <= RS232_CTS;
DCD_n <= '0';
RS232_TXD <= TXD;
-- RS232_RTS <= not RTS_n;
RS232_RTS <= RTS_n;
end process;
my_ACIA_Clock : ACIA_Clock

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