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URL https://opencores.org/ocsvn/System09/System09/trunk

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  • This comparison shows the changes necessary to convert path
    /System09/trunk/rtl/System09_Xess_XSA-3S1000
    from Rev 95 to Rev 99
    Reverse comparison

Rev 95 → Rev 99

/my_system09.prj
1,11 → 1,10
vhdl work "common.vhd"
vhdl work "../VHDL/bit_funcs.vhd"
vhdl work "../VHDL/ACIA_Clock.vhd"
vhdl work "../Spartan3/keymap_rom_slice.vhd"
vhdl work "../Spartan3/keymap_rom512_b4.vhd"
vhdl work "../../src/sys09bug/sys09xes.vhd"
vhdl work "../../src/Flex9/flex9ide.vhd"
vhdl work "../VHDL/ps2_keyboard.vhd"
vhdl work "../VHDL/ACIA_TX.vhd"
vhdl work "../VHDL/ACIA_RX.vhd"
vhdl work "sdramcntl.vhd"
vhdl work "../Spartan3/ram2k_b16.vhd"
vhdl work "../Spartan3/char_rom2k_b16.vhd"
15,6 → 14,6
vhdl work "../VHDL/keyboard.vhd"
vhdl work "../VHDL/datram.vhd"
vhdl work "../VHDL/cpu09.vhd"
vhdl work "../VHDL/ACIA_6850.vhd"
vhdl work "../VHDL/acia6850.vhd"
vhdl work "xsasdramcntl.vhd"
vhdl work "System09_Xess_XSA-3S1000.vhd"
/System09_Xess_XSA-3S1000.vhd
26,9 → 26,7
--
-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
-- cpu09 (cpu09.vhd) CPU core
-- ACIA_6850 (ACIA_6850.vhd) ACIA / UART
-- (ACIA_RX.vhd)
-- (ACIA_TX.vhd)
-- ACIA_6850 (acia6850.vhd) ACIA / UART
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
-- keyboard (keyboard.vhd) PS/2 Keyboard interface
-- (ps2_keyboard.vhd)
367,16 → 365,16
port (
clk: in std_logic;
rst: in std_logic;
vma: out std_logic;
addr: out std_logic_vector(15 downto 0);
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_out: out std_logic_vector(7 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
firq: in std_logic;
nmi: in std_logic;
firq: in std_logic
halt: in std_logic;
hold: in std_logic
);
end component;
 
423,16 → 421,16
--
-----------------------------------------------------------------
 
component ACIA_6850
component acia6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
addr : in Std_Logic; -- Register Select
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
451,12 → 449,12
 
component ACIA_Clock
generic (
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
SYS_CLK_FREQ : integer := SYS_Clock_Frequency;
ACIA_CLK_FREQ : integer := ACIA_Clock_Frequency
);
port (
clk : in Std_Logic; -- System Clock Input
ACIA_clk : out Std_logic -- ACIA Clock output
acia_clk : out Std_logic -- ACIA Clock output
);
end component;
 
469,7 → 467,7
 
component keyboard
generic(
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
KBD_CLK_FREQ : integer := CPU_Clock_Frequency
);
port(
clk : in std_logic;
651,16 → 649,16
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_reset,
vma => cpu_vma,
addr => cpu_addr(15 downto 0),
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_out => cpu_data_out,
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
firq => cpu_firq,
nmi => cpu_nmi,
firq => cpu_firq
halt => cpu_halt,
hold => cpu_hold
);
 
my_rom : mon_rom port map (
683,15 → 681,16
data_in => cpu_data_out
);
 
my_acia : ACIA_6850 port map (
my_acia : acia6850 port map (
clk => cpu_clk,
rst => cpu_reset,
cs => acia_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => acia_data_out,
irq => acia_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => acia_data_out,
 
RxC => acia_clk,
TxC => acia_clk,
RxD => rxd,
704,8 → 703,8
 
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_Clock_Frequency => SYS_Clock_Frequency,
ACIA_Clock_Frequency => ACIA_Clock_Frequency
SYS_CLK_FREQ => SYS_Clock_Frequency,
ACIA_CLK_FREQ => ACIA_Clock_Frequency
)
port map(
clk => Clk_i,
719,7 → 718,7
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_Clock_Frequency => CPU_Clock_frequency
KBD_CLK_FREQ => CPU_Clock_frequency
)
port map(
clk => cpu_clk,

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