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https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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- This comparison shows the changes necessary to convert path
/System09/trunk
- from Rev 139 to Rev 140
- ↔ Reverse comparison
Rev 139 → Rev 140
/rtl/System09_base/my_system09.vhd
File deleted
/rtl/System09_base/system09.vhd
203,7 → 203,7
-- Slot 2 $E1C0 - $E1FF |
slot2_cs_n : out std_logic; |
-- slot2_irq : in std_logic; |
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-- CPU Debug Interface signals |
-- cpu_reset_o : out Std_Logic; |
-- cpu_clk_o : out Std_Logic; |
230,8 → 230,8
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----------------------------------------------------------------------------- |
-- constants |
----------------------------------------------------------------------------- |
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----------------------------------------------------------------------------- |
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-- SDRAM |
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz |
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) |
245,14 → 245,14
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width |
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constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock |
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock |
constant VGA_CLK_DIV : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ); |
constant BAUD_RATE : integer := 57600; -- Baud Rate |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; |
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constant TRESET : natural := 300; -- min initialization interval (us) |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; |
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constant TRESET : natural := 300; -- min initialization interval (us) |
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval |
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type hold_state_type is ( hold_release_state, hold_request_state ); |
362,16 → 362,16
signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM |
signal hRd : std_logic; -- host-side read control signal |
signal hWr : std_logic; -- host-side write control signal |
signal hUds : std_logic; -- host-side upper data strobe |
signal hLds : std_logic; -- host-side lower data strobe |
signal hUds : std_logic; -- host-side upper data strobe |
signal hLds : std_logic; -- host-side lower data strobe |
signal rdPending : std_logic; -- read operation pending in SDRAM pipeline |
type ram_type is (ram_state_0, |
ram_state_rd1, ram_state_rd2, |
ram_state_wr1, |
type ram_type is (ram_state_0, |
ram_state_rd1, ram_state_rd2, |
ram_state_wr1, |
ram_state_3 ); |
signal ram_state : ram_type; |
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-- signal BaudCount : std_logic_vector(5 downto 0); |
signal CountL : std_logic_vector(23 downto 0); |
signal clk_count : natural range 0 to CPU_CLK_DIV; |
604,8 → 604,8
data_out : out std_logic_vector(7 downto 0) |
); |
end component; |
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component XSASDRAMCntl |
generic( |
FREQ : natural := MEM_CLK_FREQ;-- operating frequency in KHz |
629,8 → 629,8
rst : in std_logic; -- reset |
rd : in std_logic; -- initiate read operation |
wr : in std_logic; -- initiate write operation |
uds : in std_logic; -- upper data strobe |
lds : in std_logic; -- lower data strobe |
uds : in std_logic; -- upper data strobe |
lds : in std_logic; -- lower data strobe |
earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) |
opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) |
rdPending : out std_logic; -- read operation(s) are still in the pipeline |
656,7 → 656,7
dqml : out std_logic -- low databits I/O mask |
); |
end component; |
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-- |
-- Clock buffer |
-- |
842,7 → 842,7
data_in => cpu_data_out, |
data_out => dat_addr(7 downto 0) |
); |
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------------------------------------------------------------------------ |
-- Instantiate the SDRAM controller that connects to the memory tester |
-- module and interfaces to the external SDRAM chip. |
849,9 → 849,9
------------------------------------------------------------------------ |
u1 : xsaSDRAMCntl |
generic map( |
FREQ => MEM_CLK_FREQ, |
FREQ => MEM_CLK_FREQ, |
CLK_DIV => SYS_CLK_DIV, |
PIPE_EN => PIPE_EN, |
PIPE_EN => PIPE_EN, |
MAX_NOP => MAX_NOP, |
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, |
DATA_WIDTH => DATA_WIDTH, |
870,8 → 870,8
rst => rst_i, -- reset |
rd => hRd, -- host-side SDRAM read control from memory tester |
wr => hWr, -- host-side SDRAM write control from memory tester |
uds => hUds, -- host-side SDRAM upper data strobe |
lds => hLds, -- host-side SDRAM lower data strobe |
uds => hUds, -- host-side SDRAM upper data strobe |
lds => hLds, -- host-side SDRAM lower data strobe |
rdPending => rdPending,-- read operation to SDRAM is in progress |
opBegun => opBegun, -- indicates memory read/write has begun |
earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun |
895,7 → 895,7
dqmh => SDRAM_dqmh, -- SDRAM DQMH |
dqml => SDRAM_dqml -- SDRAM DQML |
); |
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cpu_clk_buffer : BUFG port map( |
i => Clk25, |
o => cpu_clk |
1085,7 → 1085,7
-- ISA bus little endian |
-- Not sure about IDE interface |
-- |
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out, |
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out, |
pb_cs, pb_wreg, pb_rreg ) |
begin |
pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0)); |
1246,20 → 1246,20
my_prescaler : process( clk_i, clk_count ) |
begin |
if rising_edge( clk_i ) then |
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if clk_count = 0 then |
clk_count <= CPU_CLK_DIV-1; |
else |
clk_count <= clk_count - 1; |
end if; |
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if clk_count = 0 then |
clk25 <= '0'; |
elsif clk_count = (CPU_CLK_DIV/2) then |
clk25 <= '1'; |
if clk_count = 0 then |
clk_count <= CPU_CLK_DIV-1; |
else |
clk_count <= clk_count - 1; |
end if; |
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end if; |
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if clk_count = 0 then |
clk25 <= '0'; |
elsif clk_count = (CPU_CLK_DIV/2) then |
clk25 <= '1'; |
end if; |
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end if; |
end process; |
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-- |
1267,8 → 1267,8
-- |
my_switch_assignments : process( rst_i, SW2_N, lock ) |
begin |
rst_i <= not SW2_N; |
cpu_reset <= rst_i or (not lock); |
rst_i <= not SW2_N; |
cpu_reset <= rst_i or (not lock); |
end process; |
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-- |
1317,7 → 1317,7
VGA_blue(1) <= vga_blue_o; |
VGA_blue(2) <= vga_blue_o; |
end process; |
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-- |
-- SDRAM read write control |
-- |
1327,7 → 1327,7
ram_rd_req, ram_wr_req ) |
begin |
if( cpu_reset = '1' ) then |
hRd <= '0'; |
hRd <= '0'; |
hWr <= '0'; |
ram_hold <= '0'; |
ram_state <= ram_state_0; |
1340,13 → 1340,13
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when ram_state_0 => |
if ram_rd_req = '1' then |
ram_hold <= '1'; |
ram_hold <= '1'; |
hRd <= '1'; |
ram_state <= ram_state_rd1; |
elsif ram_wr_req = '1' then |
ram_hold <= '1'; |
hWr <= '1'; |
ram_state <= ram_state_wr1; |
ram_state <= ram_state_rd1; |
elsif ram_wr_req = '1' then |
ram_hold <= '1'; |
hWr <= '1'; |
ram_state <= ram_state_wr1; |
end if; |
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when ram_state_rd1 => |
1357,13 → 1357,13
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when ram_state_rd2 => |
if ramDone = '1' then |
ram_hold <= '0'; |
ram_hold <= '0'; |
ram_state <= ram_state_3; |
end if; |
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when ram_state_wr1 => |
if opBegun = '1' then |
ram_hold <= '0'; |
ram_hold <= '0'; |
hWr <= '0'; |
ram_state <= ram_state_3; |
end if; |
1376,35 → 1376,35
when others => |
hRd <= '0'; |
hWr <= '0'; |
ram_hold <= '0'; |
ram_hold <= '0'; |
ram_state <= ram_state_0; |
end case; |
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end if; |
end process; |
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-- |
-- SDRAM Address and data bus assignments |
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-- |
-- SDRAM Address and data bus assignments |
-- |
my_sdram_addr_data : process( cpu_addr, dat_addr, |
cpu_data_out, hDout ) |
begin |
hAddr(23 downto 19) <= "00000"; |
hAddr(18 downto 11) <= dat_addr; |
hAddr(10 downto 0) <= cpu_addr(11 downto 1); |
hUds <= not cpu_addr(0); |
hLds <= cpu_addr(0); |
if cpu_addr(0) = '0' then |
hDin( 7 downto 0) <= (others=>'0'); |
hDin(15 downto 8) <= cpu_data_out; |
ram_data_out <= hDout(15 downto 8); |
else |
hDin( 7 downto 0) <= cpu_data_out; |
hDin(15 downto 8) <= (others=>'0'); |
ram_data_out <= hDout( 7 downto 0); |
end if; |
begin |
hAddr(23 downto 19) <= "00000"; |
hAddr(18 downto 11) <= dat_addr; |
hAddr(10 downto 0) <= cpu_addr(11 downto 1); |
hUds <= not cpu_addr(0); |
hLds <= cpu_addr(0); |
if cpu_addr(0) = '0' then |
hDin( 7 downto 0) <= (others=>'0'); |
hDin(15 downto 8) <= cpu_data_out; |
ram_data_out <= hDout(15 downto 8); |
else |
hDin( 7 downto 0) <= cpu_data_out; |
hDin(15 downto 8) <= (others=>'0'); |
ram_data_out <= hDout( 7 downto 0); |
end if; |
end process; |
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-- |
-- Hold RAM until falling CPU clock edge |
-- |
1416,21 → 1416,21
ram_release <= '1'; |
end if; |
end process; |
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-- |
-- CPU read data request on rising CPU clock edge |
-- |
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release ) |
begin |
if hRd = '1' then |
if hRd = '1' then |
ram_rd_req <= '0'; |
elsif rising_edge(cpu_clk) then |
elsif rising_edge(cpu_clk) then |
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then |
ram_rd_req <= '1'; |
end if; |
ram_rd_req <= '1'; |
end if; |
end if; |
end process; |
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-- |
-- CPU write data to RAM valid on rising CPU clock edge |
-- |
1438,43 → 1438,43
begin |
if hWr = '1' then |
ram_wr_req <= '0'; |
elsif rising_edge(cpu_clk) then |
elsif rising_edge(cpu_clk) then |
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then |
ram_wr_req <= '1'; |
ram_wr_req <= '1'; |
end if; |
end if; |
end process; |
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status_leds : process( rst_i, cpu_reset, lock ) |
begin |
S(0) <= rst_i; |
S(1) <= cpu_reset; |
S(2) <= lock; |
S(3) <= countL(23); |
S(7 downto 4) <= "0000"; |
end process; |
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--debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma, |
-- cpu_halt, cpu_hold, |
-- cpu_firq, cpu_irq, cpu_nmi, |
-- cpu_addr, cpu_data_out, cpu_data_in ) |
--begin |
-- cpu_reset_o <= cpu_reset; |
-- cpu_clk_o <= cpu_clk; |
-- cpu_rw_o <= cpu_rw; |
-- cpu_vma_o <= cpu_vma; |
-- cpu_halt_o <= cpu_halt; |
-- cpu_hold_o <= cpu_hold; |
-- cpu_firq_o <= cpu_firq; |
-- cpu_irq_o <= cpu_irq; |
-- cpu_nmi_o <= cpu_nmi; |
-- cpu_addr_o <= cpu_addr; |
-- cpu_data_out_o <= cpu_data_out; |
-- cpu_data_in_o <= cpu_data_in; |
--end process; |
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status_leds : process( rst_i, cpu_reset, lock ) |
begin |
S(0) <= rst_i; |
S(1) <= cpu_reset; |
S(2) <= lock; |
S(3) <= countL(23); |
S(7 downto 4) <= "0000"; |
end process; |
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--debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma, |
-- cpu_halt, cpu_hold, |
-- cpu_firq, cpu_irq, cpu_nmi, |
-- cpu_addr, cpu_data_out, cpu_data_in ) |
--begin |
-- cpu_reset_o <= cpu_reset; |
-- cpu_clk_o <= cpu_clk; |
-- cpu_rw_o <= cpu_rw; |
-- cpu_vma_o <= cpu_vma; |
-- cpu_halt_o <= cpu_halt; |
-- cpu_hold_o <= cpu_hold; |
-- cpu_firq_o <= cpu_firq; |
-- cpu_irq_o <= cpu_irq; |
-- cpu_nmi_o <= cpu_nmi; |
-- cpu_addr_o <= cpu_addr; |
-- cpu_data_out_o <= cpu_data_out; |
-- cpu_data_in_o <= cpu_data_in; |
--end process; |
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end rtl; --===================== End of architecture =======================-- |
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