URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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- This comparison shows the changes necessary to convert path
/System09
- from Rev 181 to Rev 182
- ↔ Reverse comparison
Rev 181 → Rev 182
/trunk/src/Flex9/flex9ram.vhd
0,0 → 1,618
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
library unisim; |
use unisim.vcomponents.all; |
|
entity FLEX9_C000 is |
port( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector(10 downto 0); |
data_out : out std_logic_vector(7 downto 0); |
data_in : in std_logic_vector(7 downto 0) |
); |
end FLEX9_C000; |
|
architecture rtl of FLEX9_C000 is |
|
type data_array is array(0 to 0) of std_logic_vector(7 downto 0); |
signal xdata : data_array; |
signal en : std_logic_vector(0 downto 0); |
signal dp : std_logic_vector(0 downto 0); |
signal we : std_logic; |
|
begin |
|
ROM00: RAMB16_S9 |
generic map ( |
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000" |
) |
port map ( |
CLK => clk, |
SSR => rst, |
EN => en(0), |
WE => we, |
ADDR => addr(10 downto 0), |
DI => data_in, |
DIP(0) => dp(0), |
DO => xdata(0), |
DOP(0) => dp(0) |
); |
rom_glue: process (cs, rw, addr, xdata) |
begin |
en(0) <= cs; |
data_out <= xdata(0); |
we <= not rw; |
end process; |
end architecture rtl; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
library unisim; |
use unisim.vcomponents.all; |
|
entity FLEX9_C800 is |
port( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector(10 downto 0); |
data_out : out std_logic_vector(7 downto 0); |
data_in : in std_logic_vector(7 downto 0) |
); |
end FLEX9_C800; |
|
architecture rtl of FLEX9_C800 is |
|
type data_array is array(0 to 0) of std_logic_vector(7 downto 0); |
signal xdata : data_array; |
signal en : std_logic_vector(0 downto 0); |
signal dp : std_logic_vector(0 downto 0); |
signal we : std_logic; |
|
begin |
|
ROM00: RAMB16_S9 |
generic map ( |
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000" |
) |
port map ( |
CLK => clk, |
SSR => rst, |
EN => en(0), |
WE => we, |
ADDR => addr(10 downto 0), |
DI => data_in, |
DIP(0) => dp(0), |
DO => xdata(0), |
DOP(0) => dp(0) |
); |
rom_glue: process (cs, rw, addr, xdata) |
begin |
en(0) <= cs; |
data_out <= xdata(0); |
we <= not rw; |
end process; |
end architecture rtl; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
library unisim; |
use unisim.vcomponents.all; |
|
entity FLEX9_D000 is |
port( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector(10 downto 0); |
data_out : out std_logic_vector(7 downto 0); |
data_in : in std_logic_vector(7 downto 0) |
); |
end FLEX9_D000; |
|
architecture rtl of FLEX9_D000 is |
|
type data_array is array(0 to 0) of std_logic_vector(7 downto 0); |
signal xdata : data_array; |
signal en : std_logic_vector(0 downto 0); |
signal dp : std_logic_vector(0 downto 0); |
signal we : std_logic; |
|
begin |
|
ROM00: RAMB16_S9 |
generic map ( |
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000" |
) |
port map ( |
CLK => clk, |
SSR => rst, |
EN => en(0), |
WE => we, |
ADDR => addr(10 downto 0), |
DI => data_in, |
DIP(0) => dp(0), |
DO => xdata(0), |
DOP(0) => dp(0) |
); |
rom_glue: process (cs, rw, addr, xdata) |
begin |
en(0) <= cs; |
data_out <= xdata(0); |
we <= not rw; |
end process; |
end architecture rtl; |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
library unisim; |
use unisim.vcomponents.all; |
|
entity FLEX9_D800 is |
port( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector(10 downto 0); |
data_out : out std_logic_vector(7 downto 0); |
data_in : in std_logic_vector(7 downto 0) |
); |
end FLEX9_D800; |
|
architecture rtl of FLEX9_D800 is |
|
type data_array is array(0 to 0) of std_logic_vector(7 downto 0); |
signal xdata : data_array; |
signal en : std_logic_vector(0 downto 0); |
signal dp : std_logic_vector(0 downto 0); |
signal we : std_logic; |
|
begin |
|
ROM00: RAMB16_S9 |
generic map ( |
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_30 => x"0000C3007EBF007EA7007EA3007E9F007E6C007E63007E5F007E5B007E57007E", |
INIT_31 => x"0000000000000000000000000000FFFF40100302010000000000000000000000", |
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000", |
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000" |
) |
port map ( |
CLK => clk, |
SSR => rst, |
EN => en(0), |
WE => we, |
ADDR => addr(10 downto 0), |
DI => data_in, |
DIP(0) => dp(0), |
DO => xdata(0), |
DOP(0) => dp(0) |
); |
rom_glue: process (cs, rw, addr, xdata) |
begin |
en(0) <= cs; |
data_out <= xdata(0); |
we <= not rw; |
end process; |
end architecture rtl; |
|
-- |
-- Flex9 O/S Initialised 8KByte RAM |
-- |
-- v1.0 - 22 December 2006 - John Kent |
-- v1.1 - 1 February 2008 - David Burnette |
-- reworked to use autogenerated block ram utility |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
library unisim; |
use unisim.vcomponents.all; |
|
entity flex_ram is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (12 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end flex_ram; |
|
architecture rtl of flex_ram is |
|
signal we : std_logic; |
signal cs0 : std_logic; |
signal cs1 : std_logic; |
signal cs2 : std_logic; |
signal cs3 : std_logic; |
signal dp0 : std_logic; |
signal dp1 : std_logic; |
signal dp2 : std_logic; |
signal dp3 : std_logic; |
signal rdata0 : std_logic_vector(7 downto 0); |
signal rdata1 : std_logic_vector(7 downto 0); |
signal rdata2 : std_logic_vector(7 downto 0); |
signal rdata3 : std_logic_vector(7 downto 0); |
|
component FLEX9_C000 |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end component; |
component FLEX9_C800 |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end component; |
component FLEX9_D000 |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end component; |
component FLEX9_D800 |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_out : out std_logic_vector (7 downto 0); |
data_in : in std_logic_vector (7 downto 0) |
); |
end component; |
|
begin |
|
addr_c000 : FLEX9_C000 port map ( |
clk => clk, |
rst => rst, |
cs => cs0, |
rw => rw, |
addr => addr(10 downto 0), |
data_in => data_in, |
data_out => rdata0 |
); |
|
addr_c800 : FLEX9_C800 port map ( |
clk => clk, |
rst => rst, |
cs => cs1, |
rw => rw, |
addr => addr(10 downto 0), |
data_in => data_in, |
data_out => rdata1 |
); |
addr_d000 : FLEX9_D000 port map ( |
clk => clk, |
rst => rst, |
cs => cs2, |
rw => rw, |
addr => addr(10 downto 0), |
data_in => data_in, |
data_out => rdata2 |
); |
addr_d800 : FLEX9_D800 port map ( |
clk => clk, |
rst => rst, |
cs => cs3, |
rw => rw, |
addr => addr(10 downto 0), |
data_in => data_in, |
data_out => rdata3 |
); |
|
my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 ) |
begin |
we <= not rw; |
case addr(12 downto 11) is |
when "00" => |
cs0 <= cs; |
cs1 <= '0'; |
cs2 <= '0'; |
cs3 <= '0'; |
data_out <= rdata0; |
when "01" => |
cs0 <= '0'; |
cs1 <= cs; |
cs2 <= '0'; |
cs3 <= '0'; |
data_out <= rdata1; |
when "10" => |
cs0 <= '0'; |
cs1 <= '0'; |
cs2 <= cs; |
cs3 <= '0'; |
data_out <= rdata2; |
when "11" => |
cs0 <= '0'; |
cs1 <= '0'; |
cs2 <= '0'; |
cs3 <= cs; |
data_out <= rdata3; |
when others => |
null; |
end case; |
|
end process; |
|
end architecture rtl; |
|