URL
https://opencores.org/ocsvn/altor32/altor32/trunk
Subversion Repositories altor32
Compare Revisions
- This comparison shows the changes necessary to convert path
/altor32/trunk
- from Rev 41 to Rev 42
- ↔ Reverse comparison
Rev 41 → Rev 42
/sw/common/serial.c
0,0 → 1,63
#include "mem_map.h" |
#include "serial.h" |
|
//----------------------------------------------------------------- |
// Defines |
//----------------------------------------------------------------- |
#define UART_RX_AVAIL (1<<0) |
#define UART_TX_BUSY (1<<3) |
|
//------------------------------------------------------------- |
// serial_init: |
//------------------------------------------------------------- |
void serial_init (void) |
{ |
// Not required |
} |
//------------------------------------------------------------- |
// serial_putchar: Write character to UART Tx buffer |
//------------------------------------------------------------- |
int serial_putchar(char ch) |
{ |
if (ch == '\n') |
serial_putchar('\r'); |
|
// Print in simulator via l.nop instruction |
{ |
register char t1 asm ("r3") = ch; |
asm volatile ("\tl.nop\t%0" : : "K" (0x0004), "r" (t1)); |
} |
|
// Write to Tx buffer |
UART_UDR = ch; |
|
// Wait for Tx to complete |
while (UART_USR & UART_TX_BUSY); |
|
return 0; |
} |
//------------------------------------------------------------- |
// serial_getchar: Read character from UART Rx buffer |
//------------------------------------------------------------- |
int serial_getchar (void) |
{ |
if (serial_haschar()) |
return UART_UDR; |
else |
return -1; |
} |
//------------------------------------------------------------- |
// serial_haschar: Is a character waiting in Rx buffer |
//------------------------------------------------------------- |
int serial_haschar() |
{ |
return (UART_USR & UART_RX_AVAIL); |
} |
//------------------------------------------------------------- |
// serial_putstr: Send a string to UART |
//------------------------------------------------------------- |
void serial_putstr(char *str) |
{ |
while (*str) |
serial_putchar(*str++); |
} |
/sw/common/irq.h
0,0 → 1,11
#ifndef __IRQ_H__ |
#define __IRQ_H__ |
|
//----------------------------------------------------------------- |
// Prototypes |
//----------------------------------------------------------------- |
void irq_enable(int interrupt); |
void irq_disable(int interrupt); |
void irq_acknowledge(int interrupt); |
|
#endif |
/sw/common/mem_map.h
0,0 → 1,49
#ifndef __MEM_MAP_H__ |
#define __MEM_MAP_H__ |
|
//----------------------------------------------------------------- |
// Defines: |
//----------------------------------------------------------------- |
#define IO_BASE 0x12000000 |
|
//----------------------------------------------------------------- |
// Macros: |
//----------------------------------------------------------------- |
#define REG8 (volatile unsigned char*) |
#define REG16 (volatile unsigned short*) |
#define REG32 (volatile unsigned int*) |
|
//----------------------------------------------------------------- |
// Peripheral Base Addresses |
//----------------------------------------------------------------- |
#define UART_BASE (IO_BASE + 0x000) |
#define TIMER_BASE (IO_BASE + 0x100) |
#define INTR_BASE (IO_BASE + 0x200) |
|
//----------------------------------------------------------------- |
// Interrupts |
//----------------------------------------------------------------- |
#define IRQ_UART_RX 0 |
#define IRQ_TIMER_SYSTICK 1 |
#define IRQ_TIMER_HIRES 2 |
#define IRQ_EXT_INT0 8 |
|
//----------------------------------------------------------------- |
// Peripheral Registers |
//----------------------------------------------------------------- |
|
// UART |
#define UART_USR (*(REG32 (UART_BASE + 0x4))) |
#define UART_UDR (*(REG32 (UART_BASE + 0x8))) |
|
// TIMER |
#define TIMER_VAL (*(REG32 (TIMER_BASE + 0x0))) |
#define SYS_CLK_COUNT (*(REG32 (TIMER_BASE + 0x4))) |
|
// IRQ |
#define IRQ_MASK (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_SET (*(REG32 (INTR_BASE + 0x00))) |
#define IRQ_MASK_CLR (*(REG32 (INTR_BASE + 0x04))) |
#define IRQ_STATUS (*(REG32 (INTR_BASE + 0x08))) |
|
#endif |
/sw/common/timer.c
0,0 → 1,20
#include "mem_map.h" |
#include "timer.h" |
|
//-------------------------------------------------------------------------- |
// timer_init: |
//-------------------------------------------------------------------------- |
void timer_init(void) |
{ |
// Not required |
} |
//-------------------------------------------------------------------------- |
// timer_sleep: |
//-------------------------------------------------------------------------- |
void timer_sleep(int timeMs) |
{ |
t_time t = timer_now(); |
|
while (timer_diff(timer_now(), t) < timeMs) |
; |
} |
/sw/common/cache.c
0,0 → 1,50
#include "cache.h" |
|
//----------------------------------------------------------------- |
// Defines: |
//----------------------------------------------------------------- |
// SR Register |
#define SPR_SR (17) |
#define SPR_SR_ICACHE_FLUSH (1 << 17) |
#define SPR_SR_DCACHE_FLUSH (1 << 18) |
|
//----------------------------------------------------------------- |
// mfspr: Read from SPR |
//----------------------------------------------------------------- |
static inline unsigned long mfspr(unsigned long spr) |
{ |
unsigned long value; |
asm volatile ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); |
return value; |
} |
//----------------------------------------------------------------- |
// mtspr: Write to SPR |
//----------------------------------------------------------------- |
static inline void mtspr(unsigned long spr, unsigned long value) |
{ |
asm volatile ("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); |
} |
//----------------------------------------------------------------- |
// cache_dflush: |
//----------------------------------------------------------------- |
void cache_dflush(void) |
{ |
unsigned long sr = mfspr(SPR_SR); |
mtspr(SPR_SR, sr | SPR_SR_DCACHE_FLUSH); |
} |
//----------------------------------------------------------------- |
// cache_iflush: |
//----------------------------------------------------------------- |
void cache_iflush(void) |
{ |
unsigned long sr = mfspr(SPR_SR); |
mtspr(SPR_SR, sr | SPR_SR_ICACHE_FLUSH); |
} |
//----------------------------------------------------------------- |
// cache_flush: |
//----------------------------------------------------------------- |
void cache_flush(void) |
{ |
unsigned long sr = mfspr(SPR_SR); |
mtspr(SPR_SR, sr | SPR_SR_ICACHE_FLUSH | SPR_SR_DCACHE_FLUSH); |
} |
/sw/common/serial.h
0,0 → 1,13
#ifndef __SERIAL_H__ |
#define __SERIAL_H__ |
|
//----------------------------------------------------------------- |
// Prototypes: |
//----------------------------------------------------------------- |
void serial_init (void); |
int serial_putchar(char ch); |
int serial_getchar(void); |
int serial_haschar(); |
void serial_putstr(char *str); |
|
#endif // __SERIAL_H__ |
/sw/common/timer.h
0,0 → 1,21
#ifndef __TIMER_H__ |
#define __TIMER_H__ |
|
#include "mem_map.h" |
|
//----------------------------------------------------------------- |
// Defines: |
//----------------------------------------------------------------- |
typedef unsigned long t_time; |
|
//----------------------------------------------------------------- |
// Prototypes: |
//----------------------------------------------------------------- |
|
// General timer |
void timer_init(void); |
static t_time timer_now(void) { return TIMER_VAL; } |
static long timer_diff(t_time a, t_time b) { return (long)(a - b); } |
void timer_sleep(int timeMs); |
|
#endif |
/sw/common/cache.h
0,0 → 1,11
#ifndef __CACHE_H__ |
#define __CACHE_H__ |
|
//----------------------------------------------------------------- |
// Prototypes: |
//----------------------------------------------------------------- |
void cache_dflush(void); |
void cache_iflush(void); |
void cache_flush(void); |
|
#endif // __CACHE_H__ |
/sw/common/irq.c
0,0 → 1,24
#include "mem_map.h" |
#include "irq.h" |
|
//----------------------------------------------------------------- |
// irq_enable |
//----------------------------------------------------------------- |
void irq_enable(int interrupt) |
{ |
IRQ_MASK_SET = (1 << interrupt); |
} |
//----------------------------------------------------------------- |
// irq_disable |
//----------------------------------------------------------------- |
void irq_disable(int interrupt) |
{ |
IRQ_MASK_CLR = (1 << interrupt); |
} |
//----------------------------------------------------------------- |
// irq_acknowledge |
//----------------------------------------------------------------- |
void irq_acknowledge(int interrupt) |
{ |
IRQ_STATUS = (1 << interrupt); |
} |