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URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

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  • This comparison shows the changes necessary to convert path 
    /altor32/trunk
    from Rev 43 to Rev 44
    ↔ Reverse comparison
  •

Rev 43 → Rev 44

/rtl/cpu/altor32.v
399,7 → 399,7
.rst_i(rst_i),
 
.intr_i(intr_i),
.nmi_i(nmi_i),
.break_i(nmi_i),
// Status
.fault_o(fault_o),
/rtl/cpu/altor32_defs.v
164,6 → 164,8
`define SR_SUMRA 16
`define SR_ICACHE_FLUSH 17
`define SR_DCACHE_FLUSH 18
`define SR_STEP 19
`define SR_DBGEN 20
 
//-----------------------------------------------------------------
// OR32 Vectors
174,5 → 176,4
`define VECTOR_EXTINT 32'h00000300
`define VECTOR_SYSCALL 32'h00000400
`define VECTOR_TRAP 32'h00000600
`define VECTOR_NMI 32'h00000700
`define VECTOR_BUS_ERROR 32'h00000800
/rtl/cpu/altor32_exec.v
50,8 → 50,8
// Maskable interrupt
input intr_i /*verilator public*/,
 
// Unmaskable interrupt
input nmi_i /*verilator public*/,
// Break interrupt
input break_i /*verilator public*/,
 
// Fault
output reg fault_o /*verilator public*/,
194,8 → 194,7
 
reg d_mem_load_q;
 
// Delayed NMI
reg nmi_q;
reg break_q;
 
// Exception/Interrupt was last instruction
reg exc_last_q;
501,6 → 500,11
// If valid instruction, check if SR needs updating
if (execute_inst_r & ~stall_inst_r)
begin
 
// Clear step control (if not executing higher priority syscall/break)
if (!inst_sys_w && !inst_trap_w)
next_sr_r[`SR_STEP] = 1'b0;
 
case (1'b1)
inst_mtspr_w:
begin
1186,18 → 1190,21
 
fault_o <= 1'b0;
 
nmi_q <= 1'b0;
break_q <= 1'b0;
break_o <= 1'b0;
end
else
begin
// Record NMI in-case it can't be processed this cycle
if (nmi_i)
nmi_q <= 1'b1;
// Flop break request, clear when break interrupt executed
if (break_i)
break_q <= 1'b1;
 
// Reset branch request
pc_fetch_q <= 1'b0;
exc_last_q <= 1'b0;
 
break_o <= 1'b0;
 
// Update SR
sr_q <= next_sr_r;
 
1228,7 → 1235,7
exc_last_q <= 1'b1;
 
fault_o <= 1'b1;
end
end
// Exception: Syscall / Break
else if (branch_except_r)
begin
1236,7 → 1243,7
epc_q <= next_pc_r;
esr_q <= next_sr_r;
 
// Disable further interrupts
// Disable further interrupts / break events
sr_q <= 32'b0;
 
// Set PC to exception vector
1243,37 → 1250,41
pc_branch_q <= branch_target_r;
pc_fetch_q <= 1'b1;
exc_last_q <= 1'b1;
 
if (inst_trap_w)
break_o <= 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" Exception 0x%08x", branch_target_r);
`endif
end
// Non-maskable interrupt
else if (nmi_i | nmi_q)
// Single step / break request
else if ((sr_q[`SR_STEP] || break_q) && sr_q[`SR_DBGEN])
begin
nmi_q <= 1'b0;
 
// Save PC of next instruction
if (branch_r)
epc_q <= branch_target_r;
epc_q <= branch_target_r;
// Next expected PC (current PC + 4)
else
epc_q <= next_pc_r;
epc_q <= next_pc_r;
 
// Save SR
esr_q <= next_sr_r;
 
// Disable further interrupts
// Disable further interrupts / break events
sr_q <= 32'b0;
break_q <= 1'b0;
break_o <= 1'b1;
 
// Set PC to exception vector
pc_branch_q <= ISR_VECTOR + `VECTOR_NMI;
// Set PC to trap vector
pc_branch_q <= ISR_VECTOR + `VECTOR_TRAP;
pc_fetch_q <= 1'b1;
exc_last_q <= 1'b1;
 
`ifdef CONF_CORE_DEBUG
$display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
$display(" Break Event 0x%08x", ISR_VECTOR + `VECTOR_TRAP);
`endif
end
end
// External interrupt
else if (intr_i && next_sr_r[`SR_IEE])
begin
1286,7 → 1297,7
 
esr_q <= next_sr_r;
 
// Disable further interrupts
// Disable further interrupts / break events
sr_q <= 32'b0;
 
// Set PC to external interrupt vector
1508,15 → 1519,13
begin
if (rst_i == 1'b1)
begin
break_o <= 1'b0;
icache_flush_o <= 1'b0;
dcache_flush_o <= 1'b0;
end
else
begin
break_o <= 1'b0;
icache_flush_o <= 1'b0;
dcache_flush_o <= 1'b0;
dcache_flush_o <= 1'b0;
 
//---------------------------------------------------------------
// Valid instruction
1536,9 → 1545,6
end
endcase
end
 
inst_trap_w: // l.trap
break_o <= 1'b1;
default:
;
endcase

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