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URL https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk

Subversion Repositories artificial_neural_network

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    /artificial_neural_network
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/ANN_kernel/RTL_VHDL_files/ann.vhd
50,7 → 50,7
m_we : in std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
inputs : in std_logic_vector(NbitIn-1 downto 0); -- Input data
wdata : in std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory write data
addr : in std_logic_vector((calculate_lra_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
addr : in std_logic_vector((calculate_addr_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
 
-- Output ports
run_out : out std_logic; -- Output data validation

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