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URL https://opencores.org/ocsvn/cop/cop/trunk

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Rev 11 → Rev 12

/cop/trunk/rtl/verilog/cop_wb_bus.v
86,7 → 86,7
assign module_sel = wb_cyc_i && wb_stb_i;
assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
assign wb_racc = module_sel && !wb_we_i;
assign wb_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state;
assign wb_ack_o = SINGLE_CYCLE ? module_sel : ( module_sel && bus_wait_state);
assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
 
// generate acknowledge output signal, By using register all accesses takes two cycles.

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