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URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

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    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/cpu_lecture/trunk/src/opc_deco.vhd
290,8 → 290,12
else Q_AMOD <= AMOD_Yq;
end if;
 
Q_RD_M <= not I_OPC(9); -- '1' if LDD
Q_WE_M <= '0' & I_OPC(9); -- "01" if STD
if (I_OPC(9) = '0') then -- LDD
Q_RD_M <= I_T0 ;
Q_WE_D <= '0' & not I_T0;
else -- STD
Q_WE_M <= '0' & I_OPC(9);
end if;
 
when "100100" => -- 1001 00xx xxxx xxxx
Q_IMM <= I_OPC(31 downto 16); -- absolute address for LDS/STS
/cpu_lecture/trunk/src/opc_fetch.vhd
113,6 → 113,8
 
-- Two cycle opcodes:
--
-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
-- 1001 000d dddd .... - LDS etc.
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
122,12 → 124,15
-- 1111 111r rrrr 0bbb - SBRS
--
L_WAIT <= '0' when ((L_INVALIDATE = '1') or (I_INTVEC(5) = '1'))
else L_T0 when ((P_OPC(15 downto 9) = "1001000" ) -- LDS etc.
or ((P_OPC(15 downto 8) = "10010101") -- RET etc.
and (P_OPC(3 downto 0) /= "1010")) -- but not DEC
or ((P_OPC(15 downto 10) = "100110") -- SBIC, SBIS
and (P_OPC(8) = '1'))
or (P_OPC(15 downto 10) = "111111")) -- SBRC, SBRS
else L_T0 when ( ( (P_OPC(15 downto 14) = "10" ) -- LDD
and (P_OPC(12) = '0')
and (P_OPC( 9) = '0') )
or ( P_OPC(15 downto 9) = "1001000") -- LDS etc.
or ( ( P_OPC(15 downto 8) = "10010101") -- RET etc.
and (P_OPC( 3 downto 0) /= "1010")) -- but not DEC
or ( ( P_OPC(15 downto 10) = "100110") -- SBI[CS]
and (P_OPC(8) = '1'))
or (P_OPC(15 downto 10) = "111111")) -- SBR[CS]
else '0';
 
L_INVALIDATE <= I_CLR or I_SKIP;

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