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URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

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    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/cpu_lecture/trunk/src/opc_deco.vhd
98,7 → 98,7
--
if (I_OPC(5)) = '1' then -- interrupt
Q_ALU_OP <= ALU_INTR;
Q_AMOD <= AMOD_ddSP;
Q_AMOD <= AMOD_SPdd;
Q_JADR <= "0000000000" & I_OPC(4 downto 0) & "0";
Q_PC_OP <= PC_LD_I;
Q_WE_F <= '1';
331,7 → 331,7
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_SPi;
when "1111" => Q_AMOD <= AMOD_iSP;
when others => Q_WE_XYZS <= '0';
end case;
else -- STD / PUSH
359,7 → 359,7
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_dSP;
when "1111" => Q_AMOD <= AMOD_SPd;
when others =>
end case;
end if;
413,7 → 413,7
--
case I_OPC(7 downto 4) is
when "0000" => -- RET
Q_AMOD <= AMOD_SPii;
Q_AMOD <= AMOD_iiSP;
if (I_T0 = '1') then
Q_RD_M <= '1';
else
424,7 → 424,7
when "0001" => -- RETI
Q_ALU_OP <= ALU_INTR;
Q_IMM(6) <= '1';
Q_AMOD <= AMOD_SPii;
Q_AMOD <= AMOD_iiSP;
if (I_T0 = '1') then
Q_RD_M <= '1';
else
461,7 → 461,7
Q_PC_OP <= PC_LD_Z;
if (I_OPC(8) = '1') then -- ICALL
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_ddSP;
Q_AMOD <= AMOD_SPdd;
Q_WE_M <= "11";
Q_WE_XYZS <= '1';
end if;
492,7 → 492,7
-- kkkk kkkk kkkk kkkk
--
Q_ALU_OP <= ALU_PC_2;
Q_AMOD <= AMOD_ddSP;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
596,7 → 596,7
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_ddSP;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
/cpu_lecture/trunk/src/register_file.vhd
249,19 → 249,35
end case;
end process;
 
-- the value of the X/Y/Z/SP register after a potential PRE-decrement
-- (by 1 or 2) and POST-increment (by 1 or 2).
-- the value of the X/Y/Z/SP register after a potential PRE-inc/decrement
-- (by 1 or 2) and POST-inc/decrement (by 1 or 2).
--
process(I_AMOD(5 downto 3), I_IMM)
process(I_AMOD, I_IMM)
begin
case I_AMOD(5 downto 3) is
when AO_0 => L_PRE <= X"0000"; L_POST <= X"0000";
when AO_i => L_PRE <= X"0000"; L_POST <= X"0001";
when AO_ii => L_PRE <= X"0000"; L_POST <= X"0002";
when AO_q => L_PRE <= I_IMM; L_POST <= X"0000";
when AO_d => L_PRE <= X"FFFF"; L_POST <= X"FFFF";
when AO_dd => L_PRE <= X"FFFE"; L_POST <= X"FFFE";
when others => L_PRE <= X"0000"; L_POST <= X"0000";
case I_AMOD is
when AMOD_Xq | AMOD_Yq | AMOD_Zq =>
L_PRE <= I_IMM; L_POST <= X"0000";
 
when AMOD_Xi | AMOD_Yi | AMOD_Zi =>
L_PRE <= X"0000"; L_POST <= X"0001";
 
when AMOD_dX | AMOD_dY | AMOD_dZ =>
L_PRE <= X"FFFF"; L_POST <= X"FFFF";
 
when AMOD_iSP =>
L_PRE <= X"0001"; L_POST <= X"0001";
 
when AMOD_iiSP=>
L_PRE <= X"0001"; L_POST <= X"0002";
 
when AMOD_SPd =>
L_PRE <= X"0000"; L_POST <= X"FFFF";
 
when AMOD_SPdd=>
L_PRE <= X"FFFF"; L_POST <= X"FFFE";
 
when others =>
L_PRE <= X"0000"; L_POST <= X"0000";
end case;
end process;
 
/cpu_lecture/trunk/src/common.vhd
106,33 → 106,23
-- address modes used
--
constant AMOD_ABS : std_logic_vector(5 downto 0) := AO_0 & AS_IMM; -- IMM
constant AMOD_X : std_logic_vector(5 downto 0) := AO_0 & AS_X; -- (X)
constant AMOD_Xq : std_logic_vector(5 downto 0) := AO_Q & AS_X; -- (X+q)
constant AMOD_Xi : std_logic_vector(5 downto 0) := AO_i & AS_X; -- (X++)
constant AMOD_dX : std_logic_vector(5 downto 0) := AO_d & AS_X; -- (--X)
constant AMOD_Y : std_logic_vector(5 downto 0) := AO_0 & AS_Y; -- (Y)
constant AMOD_Yq : std_logic_vector(5 downto 0) := AO_Q & AS_Y; -- (Y+q)
constant AMOD_Yi : std_logic_vector(5 downto 0) := AO_i & AS_Y; -- (Y++)
constant AMOD_dY : std_logic_vector(5 downto 0) := AO_d & AS_Y; -- (--Y)
constant AMOD_Z : std_logic_vector(5 downto 0) := AO_0 & AS_Z; -- (Z)
constant AMOD_Zq : std_logic_vector(5 downto 0) := AO_Q & AS_Z; -- (Z+q)
constant AMOD_Zi : std_logic_vector(5 downto 0) := AO_i & AS_Z; -- (Z++)
constant AMOD_dZ : std_logic_vector(5 downto 0) := AO_d & AS_Z; -- (--Z)
constant AMOD_SPi : std_logic_vector(5 downto 0) := AO_i & AS_SP; -- (SP++)
constant AMOD_SPii: std_logic_vector(5 downto 0) := AO_ii & AS_SP; -- (SP++)
constant AMOD_dSP : std_logic_vector(5 downto 0) := AO_d & AS_SP; -- (--SP)
constant AMOD_ddSP: std_logic_vector(5 downto 0) := AO_dd & AS_SP; -- (--SP)
-----------------------------------------------------------------------
constant AMOD_X : std_logic_vector(5 downto 0) := AO_0 & AS_X; -- X
constant AMOD_Xq : std_logic_vector(5 downto 0) := AO_Q & AS_X; -- X+q
constant AMOD_Xi : std_logic_vector(5 downto 0) := AO_i & AS_X; -- X+
constant AMOD_dX : std_logic_vector(5 downto 0) := AO_d & AS_X; -- -X
constant AMOD_Y : std_logic_vector(5 downto 0) := AO_0 & AS_Y; -- Y
constant AMOD_Yq : std_logic_vector(5 downto 0) := AO_Q & AS_Y; -- Y+q
constant AMOD_Yi : std_logic_vector(5 downto 0) := AO_i & AS_Y; -- Y+
constant AMOD_dY : std_logic_vector(5 downto 0) := AO_d & AS_Y; -- -Y
constant AMOD_Z : std_logic_vector(5 downto 0) := AO_0 & AS_Z; -- Z
constant AMOD_Zq : std_logic_vector(5 downto 0) := AO_Q & AS_Z; -- Z+q
constant AMOD_Zi : std_logic_vector(5 downto 0) := AO_i & AS_Z; -- Z+
constant AMOD_dZ : std_logic_vector(5 downto 0) := AO_d & AS_Z; -- -Z
constant AMOD_iSP : std_logic_vector(5 downto 0) := AO_i & AS_SP; -- +SP
constant AMOD_iiSP: std_logic_vector(5 downto 0) := AO_ii & AS_SP; -- ++SP
constant AMOD_SPd : std_logic_vector(5 downto 0) := AO_d & AS_SP; -- SP-
constant AMOD_SPdd: std_logic_vector(5 downto 0) := AO_dd & AS_SP; -- SP--
-- Stack pointer manipulations.
--
constant SP_NOP : std_logic_vector(2 downto 0) := "000";
constant SP_ADD1: std_logic_vector(2 downto 0) := "001";
constant SP_ADD2: std_logic_vector(2 downto 0) := "010";
constant SP_SUB1: std_logic_vector(2 downto 0) := "011";
constant SP_SUB2: std_logic_vector(2 downto 0) := "100";
-----------------------------------------------------------------------
--
-- ALU multiplexers.

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