OpenCores
URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

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Rev 2 → Rev 3

/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
18,7 → 18,7
* USA
*
*
* simple implementation of DDR3 Memory
* Simple implementation of DDR3 Memory
* will only reponse to write and read request
* parameter
* count start from t0,t2,t2...
29,9 → 29,6
* | | |
* t0 t1 t2 ....
*
*2/12/2011: not able to handle multiple bank opening
*2/12/2011: not using DM signals
*
*/
 
`timescale 1ps / 1ps

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