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URL https://opencores.org/ocsvn/ddr3_synthesizable_bfm/ddr3_synthesizable_bfm/trunk

Subversion Repositories ddr3_synthesizable_bfm

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Rev 6 → Rev 7

/ddr3_synthesizable_bfm/trunk/rtl/ddr3_simple4.v
39,9 → 39,9
parameter MEM_BA_WIDTH =3,
parameter MEM_ROW_WIDTH =13,
parameter MEM_COL_WIDTH =13,
parameter MEM_AL =0,
parameter MEM_CWL =8, //CWL
parameter MEM_CL =6 //CL
parameter AL =3,
parameter CWL =5, //CWL
parameter CL =5 //CL=6 -> pass
)(
input wire [MEM_ROW_WIDTH-1:0] a,
input wire [ MEM_BA_WIDTH-1:0] ba,
61,6 → 61,8
);
 
//convert actual CL and CWL parameter to
localparam MEM_CWL=CWL+AL;
localparam MEM_CL =CL+AL;
 
//definitions
localparam OPCODE_PRECHARGE = 4'b0010;

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