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/trunk/bench/verilog/reg_int_sim.v
0,0 → 1,132
//////////////////////////////////////////////////////////////////////
//// ////
//// reg_int_sim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module reg_int_sim (
input Reset ,
input Clk_reg ,
//Tx host interface
output [4:0] Tx_Hwmark ,
output [4:0] Tx_Lwmark ,
output pause_frame_send_en ,
output [15:0] pause_quanta_set ,
output MAC_tx_add_en ,
output FullDuplex ,
output [3:0] MaxRetry ,
output [5:0] IFGset ,
output [7:0] MAC_tx_add_prom_data ,
output [2:0] MAC_tx_add_prom_add ,
output MAC_tx_add_prom_wr ,
output tx_pause_en ,
output xoff_cpu ,
output xon_cpu ,
//Rx host interface
output MAC_rx_add_chk_en ,
output [7:0] MAC_rx_add_prom_data ,
output [2:0] MAC_rx_add_prom_add ,
output MAC_rx_add_prom_wr ,
output broadcast_filter_en ,
output [15:0] broadcast_MAX ,
output RX_APPEND_CRC ,
output CRC_chk_en ,
output [5:0] RX_IFG_SET ,
output [15:0] RX_MAX_LENGTH ,// 1518
output [6:0] RX_MIN_LENGTH ,// 64
//RMON host interface
output [5:0] CPU_rd_addr ,
output CPU_rd_apply ,
input CPU_rd_grant ,
input [31:0] CPU_rd_dout ,
//Phy int host interface
output Line_loop_en ,
output [2:0] Speed ,
//MII to CPU
output [7:0] Divider ,// Divider for the host clock
output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
output [4:0] Rgad ,// Register Address (within the PHY)
output [4:0] Fiad ,// PHY Address
output NoPre ,// No Preamble (no 32-bit preamble)
output WCtrlData ,// Write Control Data operation
output RStat ,// Read Status operation
output ScanStat ,// Scan Status operation
input Busy ,// Busy Signal
input LinkFail ,// Link Integrity Signal
input Nvalid ,// Invalid Status (qualifier for the valid scan result)
input [15:0] Prsd ,// Read Status Data (data read from the PHY)
input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
);
 
assign Tx_Hwmark =5'h1e;
assign Tx_Lwmark =5'h19;
assign pause_frame_send_en =0;
assign pause_quanta_set =0;
assign MAC_tx_add_en =0;
assign FullDuplex =1;
assign MaxRetry =2;
assign IFGset =10;
assign MAC_tx_add_prom_data =0;
assign MAC_tx_add_prom_add =0;
assign MAC_tx_add_prom_wr =0;
assign tx_pause_en =0;
assign xoff_cpu =0;
assign xon_cpu =0;
assign MAC_rx_add_chk_en =0;
assign MAC_rx_add_prom_data =0;
assign MAC_rx_add_prom_add =0;
assign MAC_rx_add_prom_wr =0;
assign broadcast_filter_en =0;
assign broadcast_MAX =10;
assign RX_APPEND_CRC =0;
assign CRC_chk_en =1;
assign RX_IFG_SET =10;
assign RX_MAX_LENGTH =1518;
assign RX_MIN_LENGTH =64;
 
assign CPU_rd_addr =0;
assign CPU_rd_apply =0;
assign Line_loop_en =0;
assign Speed =3'b001;
endmodule
/trunk/bench/verilog/User_int_sim.v
0,0 → 1,121
//////////////////////////////////////////////////////////////////////
//// ////
//// User_input_sim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module User_int_sim (
input Reset ,
input Clk_user ,
//user inputerface
input Rx_mac_ra ,
output Rx_mac_rd ,
input [31:0] Rx_mac_data ,
input [1:0] Rx_mac_BE ,
input Rx_mac_pa ,
input Rx_mac_sop ,
input Rx_mac_eop ,
//user inputerface
input Tx_mac_wa ,
output Tx_mac_wr ,
output [31:0] Tx_mac_data ,
output [1:0] Tx_mac_BE ,//big endian
output Tx_mac_sop ,
output Tx_mac_eop
);
//////////////////////////////////////////////////////////////////////
// inputernal signals
//////////////////////////////////////////////////////////////////////
reg[4:0] operation;
reg[31:0] data;
reg Rx_mac_rd;
reg Start_tran;
//////////////////////////////////////////////////////////////////////
//generate Tx user data
//////////////////////////////////////////////////////////////////////
initial
begin
operation =0;
data =0;
end
 
always @ (posedge Clk_user or posedge Reset)
if (Reset)
Start_tran <=0;
else if (Tx_mac_eop&&!Tx_mac_wa)
Start_tran <=0;
else if (Tx_mac_wa)
Start_tran <=1;
always @ (posedge Clk_user )
if (Tx_mac_wa)
$ip_32W_gen("config.ini",operation,data);
else
begin
operation <=0;
data <=0;
end
 
assign Tx_mac_data =data;
assign Tx_mac_wr =operation[4];
assign Tx_mac_sop =operation[3];
assign Tx_mac_eop =operation[2];
assign Tx_mac_BE =operation[1:0];
//////////////////////////////////////////////////////////////////////
//verify Rx user data
//////////////////////////////////////////////////////////////////////
always @ (posedge Clk_user or posedge Reset)
if (Reset)
Rx_mac_rd <=0;
else if(Rx_mac_ra)
Rx_mac_rd <=1;
else
Rx_mac_rd <=0;
 
always @ (posedge Clk_user )
if (Rx_mac_pa)
$ip_32W_check( Rx_mac_data,
{Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
endmodule
/trunk/bench/verilog/tb_top.v
1,6 → 1,7
`timescale 1 ns/100ps
//////////////////////////////////////////////////////////////////////
//// ////
//// tb_top.v ////
//// tb_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
38,7 → 39,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
module tb_top (
);
46,104 → 50,135
//internal signals
//******************************************************************************
//system signals
input Reset ,
input Clk_125M ,
input Clk_user ,
input Clk_reg ,
reg Reset ;
reg Clk_125M ;
reg Clk_user ;
reg Clk_reg ;
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
wire Rx_mac_ra ;
wire Rx_mac_rd ;
wire [31:0] Rx_mac_data ;
wire [1:0] Rx_mac_BE ;
wire Rx_mac_pa ;
wire Rx_mac_sop ;
wire Rx_mac_eop ;
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
wire Tx_mac_wa ;
wire Tx_mac_wr ;
wire [31:0] Tx_mac_data ;
wire [1:0] Tx_mac_BE ;//big endian
wire Tx_mac_sop ;
wire Tx_mac_eop ;
//Phy interface
//Phy interface
output Gtx_clk ,//used only in GMII mode
input Rx_clk ,
input Tx_clk ,//used only in MII mode
output Tx_er ,
output Tx_en ,
output [7:0] Txd ,
input Rx_er ,
input Rx_dv ,
input [7:0] Rxd ,
input Crs ,
input Col ,
wire Gtx_clk ;//used only in GMII mode
wire Rx_clk ;
wire Tx_clk ;//used only in MII mode
wire Tx_er ;
wire Tx_en ;
wire [7:0] Txd ;
wire Rx_er ;
wire Rx_dv ;
wire [7:0] Rxd ;
wire Crs ;
wire Col ;
//Tx host interface
input [4:0] Tx_Hwmark ,
input [4:0] Tx_Lwmark ,
input pause_frame_send_en ,
input [15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input [3:0] MaxRetry ,
input [5:0] IFGset ,
input [7:0] MAC_tx_add_prom_data ,
input [2:0] MAC_tx_add_prom_add ,
input MAC_tx_add_prom_wr ,
input tx_pause_en ,
input xoff_cpu ,
input xon_cpu ,
wire [4:0] Tx_Hwmark ;
wire [4:0] Tx_Lwmark ;
wire pause_frame_send_en ;
wire [15:0] pause_quanta_set ;
wire MAC_tx_add_en ;
wire FullDuplex ;
wire [3:0] MaxRetry ;
wire [5:0] IFGset ;
wire [7:0] MAC_tx_add_prom_data ;
wire [2:0] MAC_tx_add_prom_add ;
wire MAC_tx_add_prom_wr ;
wire tx_pause_en ;
wire xoff_cpu ;
wire xon_cpu ;
//Rx host interface
input MAC_rx_add_chk_en ,
input [7:0] MAC_rx_add_prom_data ,
input [2:0] MAC_rx_add_prom_add ,
input MAC_rx_add_prom_wr ,
input broadcast_filter_en ,
input [15:0] broadcast_MAX ,
input RX_APPEND_CRC ,
input CRC_chk_en ,
input [5:0] RX_IFG_SET ,
input [15:0] RX_MAX_LENGTH ,// 1518
input [6:0] RX_MIN_LENGTH ,// 64
wire MAC_rx_add_chk_en ;
wire [7:0] MAC_rx_add_prom_data ;
wire [2:0] MAC_rx_add_prom_add ;
wire MAC_rx_add_prom_wr ;
wire broadcast_filter_en ;
wire [15:0] broadcast_MAX ;
wire RX_APPEND_CRC ;
wire CRC_chk_en ;
wire [5:0] RX_IFG_SET ;
wire [15:0] RX_MAX_LENGTH ;// 1518
wire [6:0] RX_MIN_LENGTH ;// 64
//RMON host interface
input [5:0] CPU_rd_addr ,
input CPU_rd_apply ,
output CPU_rd_grant ,
output [31:0] CPU_rd_dout ,
wire [5:0] CPU_rd_addr ;
wire CPU_rd_apply ;
wire CPU_rd_grant ;
wire [31:0] CPU_rd_dout ;
//Phy int host interface
input Line_loop_en ,
input [2:0] Speed ,
wire Line_loop_en ;
wire [2:0] Speed ;
//MII to CPU
input [7:0] Divider ,// Divider for the host clock
input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
input [4:0] Rgad ,// Register Address (within the PHY)
input [4:0] Fiad ,// PHY Address
input NoPre ,// No Preamble (no 32-bit preamble)
input WCtrlData ,// Write Control Data operation
input RStat ,// Read Status operation
input ScanStat ,// Scan Status operation
output Busy ,// Busy Signal
output LinkFail ,// Link Integrity Signal
output Nvalid ,// Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd ,// Read Status Data (data read from the PHY)
output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
wire [7:0] Divider ;// Divider for the host clock
wire [15:0] CtrlData ;// Control Data (to be written to the PHY reg.)
wire [4:0] Rgad ;// Register Address (within the PHY)
wire [4:0] Fiad ;// PHY Address
wire NoPre ;// No Preamble (no 32-bit preamble)
wire WCtrlData ;// Write Control Data operation
wire RStat ;// Read Status operation
wire ScanStat ;// Scan Status operation
wire Busy ;// Busy Signal
wire LinkFail ;// Link Integrity Signal
wire Nvalid ;// Invalid Status (qualifier for the valid scan result)
wire [15:0] Prsd ;// Read Status Data (data read from the PHY)
wire WCtrlDataStart ;// This signals resets the WCTRLDATA bit in the MIIM Command register
wire RStatStart ;// This signal resets the RSTAT BIT in the MIIM Command register
wire UpdateMIIRX_DATAReg ;// Updates MII RX_DATA register with read data
//MII interface signals
inout Mdio ,// MII Management Data In
output Mdc ,// MII Management Data Clock
wire Mdio ;// MII Management Data In
wire Mdc ;// MII Management Data Clock
 
//******************************************************************************
//internal signals
//******************************************************************************
 
initial
begin
Reset =1;
#20 Reset =0;
end
always
begin
#4 Clk_125M=0;
#4 Clk_125M=1;
end
 
always
begin
#5 Clk_user=0;
#5 Clk_user=1;
end
always
begin
#10 Clk_reg=0;
#10 Clk_reg=1;
end
 
 
initial
begin
$shm_open("tb_top.shm",,900000000,);
$shm_probe("AS");
end
 
 
MAC_top U_MAC_top(
.//system signals (//system signals ),
//system signals (//system signals ),
.Reset (Reset ),
.Clk_125M (Clk_125M ),
.Clk_user (Clk_user ),
.Clk_reg (Clk_reg ),
.//user interface (//user interface ),
//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
151,7 → 186,7
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
.//user interface (//user interface ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
158,8 → 193,8
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
.//Phy interface (//Phy interface ),
.//Phy interface (//Phy interface ),
//Phy interface (//Phy interface ),
//Phy interface (//Phy interface ),
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
171,7 → 206,7
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
.//Tx host interface (//Tx host interface ),
//Tx host interface (//Tx host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
186,7 → 221,7
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
.//Rx host interface (//Rx host interface ),
//Rx host interface (//Rx host interface ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
198,15 → 233,15
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
.//RMON host interface (//RMON host interface ),
//RMON host interface (//RMON host interface ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout ),
.//Phy int host interface (//Phy int host interface ),
//Phy int host interface (//Phy int host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed ),
.//MII to CPU (//MII to CPU ),
//MII to CPU (//MII to CPU ),
.Divider (Divider ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
222,10 → 257,99
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
.//MII interface signals (//MII interface signals ),
//MII interface signals (//MII interface signals ),
.Mdio (Mdio ),
.Mdc (Mdc )
);
 
Phy_sim U_Phy_sim (
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
.Tx_er (Tx_er ),
.Tx_en (Tx_en ),
.Txd (Txd ),
.Rx_er (Rx_er ),
.Rx_dv (Rx_dv ),
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
.Speed (Speed )
);
 
User_int_sim U_User_int_sim(
.Reset (Reset ),
.Clk_user (Clk_user ),
//user inputerface (//user inputerface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
//user inputerface (//user inputerface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop )
);
 
reg_int_sim U_reg_int_sim(
.Reset (Reset ),
.Clk_reg (Clk_reg ),
//Tx host interface (//Tx host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//Rx host interface (//Rx host interface ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_MAX (broadcast_MAX ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON host interface (//RMON host interface ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout ),
//Phy int host interface (//Phy int host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed ),
//MII to CPU (//MII to CPU ),
.Divider (Divider ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.NoPre (NoPre ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Busy (Busy ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.Prsd (Prsd ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
);
endmodule
/trunk/bench/verilog/Phy_sim.v
0,0 → 1,96
//////////////////////////////////////////////////////////////////////
//// ////
//// Phy_sim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
`timescale 1ns/100ps
 
module Phy_sim (
input Gtx_clk ,//used only in GMII mode
output Rx_clk ,
output Tx_clk ,//used only in MII mode
input Tx_er ,
input Tx_en ,
input [7:0] Txd ,
output Rx_er ,
output Rx_dv ,
output [7:0] Rxd ,
output Crs ,
output Col ,
input [2:0] Speed
);
//////////////////////////////////////////////////////////////////////
// this file used to simulate Phy.
// generate clk and loop the Tx data to Rx data
// full duplex mode can be verified on loop mode.
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// internal signals
//////////////////////////////////////////////////////////////////////
reg Clk_25m ;//used for 100 Mbps mode
reg Clk_2_5m ;//used for 10 Mbps mode
wire Rx_clk ;
wire Tx_clk ;//used only in MII mode
//////////////////////////////////////////////////////////////////////
always
begin
#20 Clk_25m=0;
#20 Clk_25m=1;
end
always
begin
#200 Clk_2_5m=0;
#200 Clk_2_5m=1;
end
 
assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
assign Rx_dv =Tx_en ;
assign Rxd =Txd ;
assign Rx_er =0 ;
assign Crs =Tx_en ;
assign Col =0 ;
 
endmodule
/trunk/rtl/verilog/MAC_tx.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module MAC_tx(
input Reset ,
input Clk ,
/trunk/rtl/verilog/RMON.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
module RMON (
Clk ,
/trunk/rtl/verilog/eth_miim.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
// Revision 1.4 2005/08/16 12:07:57 Administrator
// no message
//
/trunk/rtl/verilog/Clk_ctrl.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
module Clk_ctrl(
Reset ,
82,11 → 85,13
assign MAC_rx_clk =Rx_clk ;
 
CLK_DIV2 U_0_CLK_DIV2(
.Reset (Reset ),
.IN (Rx_clk ),
.OUT (Rx_clk_div2 )
);
 
CLK_DIV2 U_1_CLK_DIV2(
.Reset (Reset ),
.IN (Tx_clk ),
.OUT (Tx_clk_div2 )
);
/trunk/rtl/verilog/TECH/CLK_DIV2.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
 
//////////////////////////////////////////////////////////////////////
47,11 → 50,15
//////////////////////////////////////////////////////////////////////
 
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
 
always @ (posedge IN)
OUT <=!OUT;
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule
/trunk/rtl/verilog/TECH/afifo.v
0,0 → 1,329
//////////////////////////////////////////////////////////////////////
//// ////
//// afifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module afifo(
din,
wr_en,
wr_clk,
rd_en,
rd_clk,
ainit,
dout,
full,
almost_full,
empty,
wr_count,
rd_count,
rd_ack,
wr_ack);
//////////////////////////////////////////////////////
parameter DATA_WIDTH =32;
parameter ADDR_WIDTH =5;
parameter COUNT_DATA_WIDTH =5;
parameter ALMOST_FULL_DEPTH =8;
parameter BLK_RAM_TYPE ="M4K";
parameter DUAL_PORT_TYPE ="DUAL_PORT";// DUAL_PORT=simple dual port or BIDIR_DUAL_PORT=true dual_port
//////////////////////////////////////////////////////
input [DATA_WIDTH-1:0] din;
input wr_en;
input wr_clk;
input rd_en;
input rd_clk;
input ainit;
output [DATA_WIDTH-1:0] dout;
output full;
output almost_full;
output empty;
output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;
output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;
output rd_ack;
output wr_ack;
//////////////////////////////////////////////////////
//local signals
//////////////////////////////////////////////////////
reg [ADDR_WIDTH-1:0] Add_wr;
reg [ADDR_WIDTH-1:0] Add_wr_ungray;
reg [ADDR_WIDTH-1:0] Add_wr_gray;
reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;
reg [ADDR_WIDTH-1:0] Add_rd;
wire [ADDR_WIDTH-1:0] Add_rd_pluse;
reg [ADDR_WIDTH-1:0] Add_rd_gray;
reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;
reg [ADDR_WIDTH-1:0] Add_rd_ungray;
wire [ADDR_WIDTH-1:0] Add_wr_pluse;
integer i;
reg full /* synthesis syn_keep=1 */;
reg empty;
wire [ADDR_WIDTH-1:0] ff_used_wr;
wire [ADDR_WIDTH-1:0] ff_used_rd;
reg rd_ack;
reg rd_ack_tmp;
reg almost_full;
wire [DATA_WIDTH-1:0] dout_tmp;
 
//////////////////////////////////////////////////////
//Write clock domain
//////////////////////////////////////////////////////
assign wr_ack =0;
assign ff_used_wr =Add_wr-Add_rd_ungray;
 
assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
 
 
 
always @ (posedge ainit or posedge wr_clk)
if (ainit)
Add_wr_gray <=0;
else
begin
Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
end
 
 
 
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_rd_ungray =0;
else
begin
Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
 
assign Add_wr_pluse=Add_wr+1;
 
 
/*
always @ (Add_wr_pluse or Add_rd_ungray)
if (Add_wr_pluse==Add_rd_ungray)
full =1;
else
full =0;
 
*/
always @ (posedge wr_clk or posedge ainit)
if (ainit)
full <=0;
else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
full <=1;
else if(Add_wr!=Add_rd_ungray)
full <=0;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
almost_full <=0;
else if (wr_count>=ALMOST_FULL_DEPTH)
almost_full <=1;
else
almost_full <=0;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_wr <=0;
else if (wr_en&&!full)
Add_wr <=Add_wr +1;
//******************************************************************************
//read clock domain
//******************************************************************************
always @ (posedge rd_clk or posedge ainit)
if (ainit)
rd_ack <=0;
else if (rd_en&&!empty)
rd_ack <=1;
else
rd_ack <=0;
 
 
 
assign ff_used_rd =Add_wr_ungray-Add_rd;
assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
assign Add_rd_pluse =Add_rd+1;
 
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_rd <=0;
 
Add_rd <=Add_rd + 1;
 
 
always @ (posedge ainit or posedge rd_clk)
if (ainit)
Add_rd_gray <=0;
else
begin
Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
end
/* Add_rd_gray <={ Add_rd[8],
Add_rd[8]^Add_rd[7],
Add_rd[7]^Add_rd[6],
Add_rd[6]^Add_rd[5],
Add_rd[5]^Add_rd[4],
Add_rd[4]^Add_rd[3],
Add_rd[3]^Add_rd[2],
Add_rd[2]^Add_rd[1],
Add_rd[1]^Add_rd[0]};
*/
 
 
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_wr_ungray =0;
else
begin
Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
end
 
/* Add_wr_ungray <={
Add_wr_gray_dl1[8],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
*/
 
/*
always @ (Add_rd or Add_wr_ungray)
if (Add_rd==Add_wr_ungray)
empty =1;
else
empty =0;
*/
always @ (posedge rd_clk or posedge ainit)
if (ainit)
empty <=1;
else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
empty <=1;
else if (Add_rd!=Add_wr_ungray)
empty <=0;
 
//////////////////////////////////////////////////////
//instant need change for your own dpram
//////////////////////////////////////////////////////
duram #(
DATA_WIDTH,
ADDR_WIDTH,
BLK_RAM_TYPE,
DUAL_PORT_TYPE)
U_duram (
.data_a (din ),
.wren_a (wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (wr_clk ),
.clock_b (rd_clk ),
.q_b (dout ));
 
endmodule
/trunk/rtl/verilog/TECH/duram.v
0,0 → 1,128
//////////////////////////////////////////////////////////////////////
//// ////
//// duram.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b); //synthesis syn_black_box
 
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter BLK_RAM_TYPE = "AUTO";
parameter DURAM_MODE = "BIDIR_DUAL_PORT";
parameter ADDR_DEPTH = 2**ADDR_WIDTH;
 
 
 
input [DATA_WIDTH -1:0] data_a;
input wren_a;
input [ADDR_WIDTH -1:0] address_a;
input clock_a;
output [DATA_WIDTH -1:0] q_a;
input [DATA_WIDTH -1:0] data_b;
input wren_b;
input [ADDR_WIDTH -1:0] address_b;
input clock_b;
output [DATA_WIDTH -1:0] q_b;
 
altsyncram U_altsyncram (
.wren_a (wren_a),
.wren_b (wren_b),
.data_a (data_a),
.data_b (data_b),
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.q_a (q_a),
.q_b (q_b),
// synopsys translate_off
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.rden_b ()
// synopsys translate_on
);
defparam
U_altsyncram.intended_device_family = "Stratix",
U_altsyncram.ram_block_type = BLK_RAM_TYPE,
U_altsyncram.operation_mode = DURAM_MODE,
U_altsyncram.width_a = DATA_WIDTH,
U_altsyncram.widthad_a = ADDR_WIDTH,
// U_altsyncram.numwords_a = 256,
U_altsyncram.width_b = DATA_WIDTH,
U_altsyncram.widthad_b = ADDR_WIDTH,
// U_altsyncram.numwords_b = 256,
U_altsyncram.lpm_type = "altsyncram",
U_altsyncram.width_byteena_a = 1,
U_altsyncram.width_byteena_b = 1,
U_altsyncram.outdata_reg_a = "UNREGISTERED",
U_altsyncram.outdata_aclr_a = "NONE",
U_altsyncram.outdata_reg_b = "UNREGISTERED",
U_altsyncram.indata_aclr_a = "NONE",
U_altsyncram.wrcontrol_aclr_a = "NONE",
U_altsyncram.address_aclr_a = "NONE",
U_altsyncram.indata_reg_b = "CLOCK1",
U_altsyncram.address_reg_b = "CLOCK1",
U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1",
U_altsyncram.indata_aclr_b = "NONE",
U_altsyncram.wrcontrol_aclr_b = "NONE",
U_altsyncram.address_aclr_b = "NONE",
U_altsyncram.outdata_aclr_b = "NONE",
U_altsyncram.power_up_uninitialized = "FALSE";
endmodule
 
 
/trunk/rtl/verilog/TECH/CLK_SWITCH.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
 
//////////////////////////////////////////////////////////////////////
/trunk/rtl/verilog/MAC_top.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
module MAC_top(
//system signals
/trunk/rtl/verilog/MAC_rx/CRC_chk.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module CRC_chk(
Reset ,
114,6 → 117,6
else if (CRC_en)
CRC_reg <=NextCRC(CRC_data,CRC_reg);
 
assign CRC_err = CRC_chk_en&(Next_CRC[31:0] != 32'hc704dd7b);
assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
 
endmodule
/trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
37,8 → 37,10
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_ctrl (
Reset ,
121,6 → 123,7
parameter State_preamble =4'd01;
parameter State_SFD =4'd02;
parameter State_data =4'd03;
parameter State_checkCRC =4'd04;
parameter State_OkEnd =4'd07;
parameter State_drop =4'd08;
parameter State_ErrEnd =4'd09;
222,18 → 225,21
else
Next_state =State_data;
State_data:
if (!Crs_dv&&!CRC_err&&!Too_short&&!Too_long)
Next_state =State_OkEnd;
if (!Crs_dv&&!Too_short&&!Too_long)
Next_state =State_checkCRC;
else if (!Crs_dv&&(Too_short||Too_long))
Next_state =State_ErrEnd;
else if (!Crs_dv&&CRC_err)
Next_state =State_CRCErrEnd;
else if (Fifo_full)
Next_state =State_FFFullErrEnd;
else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
Next_state =State_drop;
else
Next_state =State_data;
Next_state =State_data;
State_checkCRC:
if (CRC_err)
Next_state =State_CRCErrEnd;
else
Next_state =State_OkEnd;
State_drop:
if (!Crs_dv)
Next_state =State_ErrEnd;
319,7 → 325,7
if (Reset)
Frame_length_counter <=0;
else if (Current_state==State_SFD)
Frame_length_counter <=0;
Frame_length_counter <=1;
else if (Current_state==State_data)
Frame_length_counter <=Frame_length_counter+ 1;
/trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v
38,7 → 38,11
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_FF (
Reset ,
140,6 → 144,9
reg Packet_number_add_dl1;
reg Packet_number_add_dl2;
reg Packet_number_add ;
reg Packet_number_add_tmp ;
reg Packet_number_add_tmp_dl1;
reg Packet_number_add_tmp_dl2;
 
reg Rx_mac_sop_tmp_dl1;
reg[35:0] Dout_dl1;
309,16 → 316,10
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
Fifo_data_byte1 <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte0 <=0;
else if (Current_state==State_byte0&&Fifo_data_en_dl1)
Fifo_data_byte0 <=Fifo_data_dl1;
always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 or Fifo_data_byte0 )
always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 )
case (Current_state)
State_be0:
Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
State_be1:
Din ={4'b1001,Fifo_data_byte3,24'h0};
State_be2:
326,7 → 327,7
State_be3:
Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
default:
Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
endcase
always @ (Current_state or Fifo_data_en)
339,9 → 340,32
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
Packet_number_add_tmp <=0;
else if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3)
Packet_number_add_tmp <=1;
else
Packet_number_add_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
begin
Packet_number_add_tmp_dl1 <=0;
Packet_number_add_tmp_dl2 <=0;
end
else
begin
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
end
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
Packet_number_add <=1;
else
Packet_number_add <=0;
/trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_rx_add_chk (
Reset ,
/trunk/rtl/verilog/MAC_rx/Broadcast_filter.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module Broadcast_filter (
Reset ,
/trunk/rtl/verilog/MAC_tx/flow_ctrl.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module flow_ctrl
(
/trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_tx_addr_add (
Reset ,
/trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
38,7 → 38,11
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_tx_ctrl (
Reset ,
242,8 → 246,7
IPLengthCounter <=0;
else if (Current_state==StateSwitchNext)
IPLengthCounter <=0;
else if (IPLengthCounter!=8'hff&&((Current_state==StateData)||
(PADCounter==0&&Current_state==StatePAD)))
else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StatePAD))
IPLengthCounter <=IPLengthCounter+1;
 
always @(posedge Clk or posedge Reset)
312,7 → 315,7
Next_state=StateJam;
else if (Fifo_data_err_empty)
Next_state=StateFFEmptyDrop;
else if (Fifo_eop&&IPLengthCounter>=60)//IP+MAC+TYPE=60
else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
Next_state=StateFCS;
else if (Fifo_eop)
Next_state=StatePAD;
321,7 → 324,7
StatePAD:
if (!FullDuplex&&Collision)
Next_state=StateJam;
else if (IPLengthCounter>=60)
else if (IPLengthCounter>=59)
Next_state=StateFCS;
else
Next_state=Current_state;
472,7 → 475,7
StateSFD:
TxD_tmp =8'hd5;
StateData:
if (Src_MAC_ptr)
if (Src_MAC_ptr&&MAC_tx_add_en)
TxD_tmp =MAC_tx_addr_data;
else
TxD_tmp =Fifo_data;
523,7 → 526,7
if (Reset)
Tx_pkt_length_rmon <=0;
else if (Current_state==StateSFD)
Tx_pkt_length_rmon <=4;
Tx_pkt_length_rmon <=0;
else if (Current_state==StateData)
Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;
553,7 → 556,7
if (Reset)
MAC_header_slot_tmp <=0;
else if(Current_state==StateSFD&&Next_state==StateData)
MAC_header_slot_tmp <=1;
MAC_header_slot_tmp <=0;
else
MAC_header_slot_tmp <=0;
/trunk/rtl/verilog/MAC_tx/CRC_gen.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module CRC_gen (
Reset ,
/trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v
38,7 → 38,11
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module MAC_tx_FF (
Reset ,
98,10 → 102,7
parameter MAC_byte2 =4'd01;
parameter MAC_byte1 =4'd02;
parameter MAC_byte0 =4'd03;
parameter MAC_BE0 =4'd04;
parameter MAC_BE3 =4'd05;
parameter MAC_BE2 =4'd06;
parameter MAC_BE1 =4'd07;
parameter MAC_wait_finish =4'd04;
parameter MAC_retry =4'd08;
parameter MAC_idle =4'd09;
parameter MAC_FFEmpty =4'd10;
213,8 → 214,14
else
Next_state_SYS =Current_state_SYS ;
SYS_EOP_ok:
if (Tx_mac_wr&&Tx_mac_sop)
Next_state_SYS =SYS_SOP;
else
Next_state_SYS =SYS_idle;
SYS_EOP_err:
if (Tx_mac_wr&&Tx_mac_sop)
Next_state_SYS =SYS_SOP;
else
Next_state_SYS =SYS_idle;
SYS_SOP_err:
Next_state_SYS =SYS_DROP;
411,7 → 418,7
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_ra_tmp <=0;
else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Hwmark)
else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark)
Fifo_ra_tmp <=1;
else
Fifo_ra_tmp <=0;
499,9 → 506,9
MAC_byte3:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
else if (Fifo_eop)
Next_state_MAC=MAC_wait_finish;
else if (Fifo_rd&&!Fifo_eop)
Next_state_MAC=MAC_byte2;
else
Next_state_MAC=Current_state_MAC;
508,9 → 515,9
MAC_byte2:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
else if (Fifo_eop)
Next_state_MAC=MAC_wait_finish;
else if (Fifo_rd&&!Fifo_eop)
Next_state_MAC=MAC_byte1;
else
Next_state_MAC=Current_state_MAC;
517,25 → 524,30
MAC_byte1:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
else if (Fifo_eop)
Next_state_MAC=MAC_wait_finish;
else if (Fifo_rd&&!Fifo_eop)
Next_state_MAC=MAC_byte0;
else
Next_state_MAC=Current_state_MAC;
MAC_byte0:
if (Empty&&Fifo_rd)
if (Empty&&Fifo_rd&&!Fifo_eop)
Next_state_MAC=MAC_FFEmpty;
else if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
else if (Fifo_eop)
Next_state_MAC=MAC_wait_finish;
else if (Fifo_rd&&!Fifo_eop)
Next_state_MAC=MAC_byte3;
else
Next_state_MAC=Current_state_MAC;
MAC_retry:
Next_state_MAC=MAC_idle;
MAC_wait_finish:
if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else
Next_state_MAC=Current_state_MAC;
MAC_pkt_sub:
Next_state_MAC=MAC_idle;
MAC_FFEmpty:
682,10 → 694,12
else
Fifo_rd_dl1 <=Fifo_rd;
always @ (Current_state_MAC or Fifo_rd_dl1)
if (Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||
Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)
Fifo_da =Fifo_rd_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_da <=0;
else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||
Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop)
Fifo_da <=1;
else
Fifo_da =0;
 
/trunk/rtl/verilog/MAC_tx/Ramdon_gen.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
 
module Ramdon_gen(
Reset ,
/trunk/rtl/verilog/RMON/RMON_addr_gen.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module RMON_addr_gen(
Clk ,
Reset ,
/trunk/rtl/verilog/RMON/RMON_ctrl.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module RMON_CTRL (
Clk ,
Reset ,
/trunk/rtl/verilog/miim/eth_shiftreg.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:47 Administrator
// no message
//
/trunk/rtl/verilog/miim/eth_outputcontrol.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
/trunk/rtl/verilog/miim/eth_clockgen.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:45 Administrator
// no message
//
/trunk/rtl/verilog/miim/timescale.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
/trunk/rtl/verilog/MAC_rx.v
38,7 → 38,10
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module MAC_rx (
input Reset ,
input Clk_user,
/trunk/rtl/verilog/Phy_int.v
38,7 → 38,13
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/13 12:15:36 Administrator
// no message
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
 
module Phy_int (
Reset ,
102,6 → 108,7
reg [7:0] MRxD ;
reg Rx_er_dl1 ;
reg Rx_dv_dl1 ;
reg Rx_dv_dl2 ;
reg [7:0] Rxd_dl1 ;
reg [7:0] Rxd_dl2 ;
reg Crs_dl1 ;
147,7 → 154,9
if (Reset)
Tx_en <=0;
else if(MTxEn_dl1)
Tx_en <=MTxEn_dl1;
Tx_en <=1;
else
Tx_en <=0;
 
assign Tx_er=0;
 
160,6 → 169,7
begin
Rx_er_dl1 <=0;
Rx_dv_dl1 <=0;
Rx_dv_dl2 <=0 ;
Rxd_dl1 <=0;
Rxd_dl2 <=0;
Crs_dl1 <=0;
169,6 → 179,7
begin
Rx_er_dl1 <=Rx_er ;
Rx_dv_dl1 <=Rx_dv ;
Rx_dv_dl2 <=Rx_dv_dl1 ;
Rxd_dl1 <=Rxd ;
Rxd_dl2 <=Rxd_dl1 ;
Crs_dl1 <=Crs ;
175,8 → 186,6
Col_dl1 <=Col ;
end
 
assign MRxErr =Rx_er_dl1 ;
assign MCRS =Crs_dl1 ;
 
185,7 → 194,7
MCrs_dv <=0;
else if(Line_loop_en)
MCrs_dv <=Tx_en;
else if(Rx_dv_dl1)
else if(Rx_dv_dl2)
MCrs_dv <=1;
else
MCrs_dv <=0;
203,8 → 212,8
MRxD <=0;
else if(Line_loop_en)
MRxD <=Txd;
else if(Speed[2]&&Rx_dv_dl1)
MRxD <=Rxd_dl1;
else if(Speed[2]&&Rx_dv_dl2)
MRxD <=Rxd_dl2;
else if(Rx_dv_dl1&&Rx_odd_data_ptr)
MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
/trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list
0,0 → 1,38
../../../../rtl/verilog/TECH/CLK_SWITCH.v
../../../../rtl/verilog/TECH/CLK_DIV2.v
../../../../rtl/verilog/TECH/duram.v
../../../../rtl/verilog/TECH/afifo.v
 
../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v
../../../../rtl/verilog/MAC_tx/Ramdon_gen.v
../../../../rtl/verilog/MAC_tx/CRC_gen.v
../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
../../../../rtl/verilog/MAC_tx/flow_ctrl.v
 
../../../../rtl/verilog/MAC_rx/CRC_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v
../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
../../../../rtl/verilog/MAC_rx/Broadcast_filter.v
 
../../../../rtl/verilog/miim/eth_clockgen.v
../../../../rtl/verilog/miim/eth_outputcontrol.v
../../../../rtl/verilog/miim/eth_shiftreg.v
 
../../../../rtl/verilog/RMON/RMON_addr_gen.v
../../../../rtl/verilog/RMON/RMON_ctrl.v
../../../../rtl/verilog/RMON/RMON_dpram.v
 
../../../../rtl/verilog/RMON.v
../../../../rtl/verilog/MAC_rx.v
../../../../rtl/verilog/MAC_tx.v
../../../../rtl/verilog/eth_miim.v
../../../../rtl/verilog/MAC_top.v
../../../../rtl/verilog/Phy_int.v
../../../../rtl/verilog/Clk_ctrl.v
 
../../../../bench/verilog/Phy_sim.v
../../../../bench/verilog/User_int_sim.v
../../../../bench/verilog/reg_int_sim.v
../../../../bench/verilog/tb_top.v
/trunk/sim/rtl_sim/ncsim_sim/bin/config.ini
0,0 → 1,3
46,1500,1,0
 
#Pkt_begin_length,Pkt_end_length,Pkt_number,Random_en
/trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll
trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc (nonexistent) +++ trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc (revision 6) @@ -0,0 +1,18 @@ +ncvlog -f vlog.list -logfile ../log/ncvlog.log + +if test $? -ne 0 +then +echo compiling err occured... +exit 1 +fi + +ncelab work.tb_top -loadvpi ip_32W_gen_vpi:PLI_register -loadvpi ip_32W_check_vpi:PLI_register -snapshot work:snap -timescale 1ns/1ps -message -access +rw -logfile ../log/ncelab.log + +if test $? -ne 0 +then +echo ncelab err occured... +exit 1 +fi + +ncsim work:snap $1 -UNBUFFERED -logfile ../log/ncsim.log -NOKEY + Index: trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll (nonexistent) +++ trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll (revision 6)
trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib (nonexistent) +++ trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib (revision 6) @@ -0,0 +1,2 @@ +DEFINE work ./worknc +INCLUDE /root/home/lib/cds.lib Index: trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var (nonexistent) +++ trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var (revision 6) @@ -0,0 +1 @@ +DEFINE WORK work Index: trunk/syn/syn.prj =================================================================== --- trunk/syn/syn.prj (nonexistent) +++ trunk/syn/syn.prj (revision 6) @@ -0,0 +1,88 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.1 +#-- Project file D:\root\home\primitive\primitive_tri_mode_mac(NA)\syn\syn.prj +#-- Written on Mon Dec 05 14:10:50 2005 + + +#add_file options +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" +add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" +add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" +add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" +add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" +add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" +add_file -verilog "../cores/afifo.v" +add_file -verilog "../cores/duram.v" +add_file -verilog "../rtl/verilog/RMON.v" +add_file -verilog "../rtl/verilog/MAC_rx.v" +add_file -verilog "../rtl/verilog/MAC_tx.v" +add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" +add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" +add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" +add_file -verilog "../rtl/verilog/miim/timescale.v" +add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v" +add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v" +add_file -verilog "../rtl/verilog/eth_miim.v" +add_file -verilog "../rtl/verilog/Clk_ctrl.v" +add_file -verilog "../rtl/verilog/Phy_int.v" +add_file -verilog "../rtl/verilog/MAC_top.v" + + +#implementation: "syn" +impl -add syn + +#device options +set_option -technology STRATIX +set_option -part EP1S10 +set_option -package FC780 +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding onehot +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 + +#map options +set_option -frequency auto +set_option -run_prop_extract 0 +set_option -fanout_limit 500 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -retiming 0 +set_option -verification_mode 0 +set_option -fixgatedclocks 0 +set_option -no_sequential_opt 0 + +#simulation options +set_option -write_verilog 1 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_file "./MAC_top.vqm" + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par +set_option -job par_1 -option run_backannotation 0 +impl -active "syn"

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