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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 111 to Rev 112
    Reverse comparison

Rev 111 → Rev 112

/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
877,6 → 881,8
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointer;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
cyc_cleared<=#Tp 1'b0;
886,6 → 892,8
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointer;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
cyc_cleared<=#Tp 1'b0;
895,6 → 903,8
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointer;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_stb_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
cyc_cleared<=#Tp 1'b0;

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