URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 116 to Rev 115
- ↔ Reverse comparison
Rev 116 → Rev 115
/trunk/bench/verilog/eth_memory.v
File deleted
/trunk/bench/verilog/tb_ethernet.v
File deleted
/trunk/bench/verilog/tb_cop.v
File deleted
/trunk/bench/verilog/eth_host.v
File deleted
/trunk/bench/verilog/tb_eth_defines.v
13,7 → 13,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/05/03 10:22:17 mohor |
// TX_BUF_BASE changed. |
// |
// Revision 1.1 2002/03/19 12:53:54 mohor |
// Some defines that are used in testbench only were moved to tb_eth_defines.v |
// file. |
60,131 → 57,6
`define BROADCAST_XFR 2 |
`define UNICAST_WRONG_XFR 3 |
|
`define ETH_BASE 32'hd0000000 |
`define ETH_WIDTH 32'h800 |
`define MEMORY_BASE 32'h2000 |
`define MEMORY_WIDTH 32'h10000 |
`define MEMORY_BASE 32'h0 |
`define TX_BUF_BASE `MEMORY_BASE |
`define RX_BUF_BASE `MEMORY_BASE + 32'h8000 |
`define TX_BD_BASE `ETH_BASE + 32'h00000400 |
`define RX_BD_BASE `ETH_BASE + 32'h00000600 |
|
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) |
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) |
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) |
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) |
|
|
|
/* Tx BD */ |
`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */ |
`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */ |
`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */ |
`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */ |
`define ETH_TX_BD_CRC 32'h0800 /* Tx BD CRC Enable */ |
|
`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */ |
`define ETH_TX_BD_RETRY 32'h00F0 /* Tx BD Retry Status */ |
`define ETH_TX_BD_RETLIM 32'h0008 /* Tx BD Retransmission Limit Status */ |
`define ETH_TX_BD_LATECOL 32'h0004 /* Tx BD Late Collision Status */ |
`define ETH_TX_BD_DEFER 32'h0002 /* Tx BD Defer Status */ |
`define ETH_TX_BD_CARRIER 32'h0001 /* Tx BD Carrier Sense Lost Status */ |
|
/* Rx BD */ |
`define ETH_RX_BD_EMPTY 32'h8000 /* Rx BD Empty */ |
`define ETH_RX_BD_IRQ 32'h4000 /* Rx BD IRQ Enable */ |
`define ETH_RX_BD_WRAP 32'h2000 /* Rx BD Wrap (last BD) */ |
|
`define ETH_RX_BD_MISS 32'h0080 /* Rx BD Miss Status */ |
`define ETH_RX_BD_OVERRUN 32'h0040 /* Rx BD Overrun Status */ |
`define ETH_RX_BD_INVSIMB 32'h0020 /* Rx BD Invalid Symbol Status */ |
`define ETH_RX_BD_DRIBBLE 32'h0010 /* Rx BD Dribble Nibble Status */ |
`define ETH_RX_BD_TOOLONG 32'h0008 /* Rx BD Too Long Status */ |
`define ETH_RX_BD_SHORT 32'h0004 /* Rx BD Too Short Frame Status */ |
`define ETH_RX_BD_CRCERR 32'h0002 /* Rx BD CRC Error Status */ |
`define ETH_RX_BD_LATECOL 32'h0001 /* Rx BD Late Collision Status */ |
|
|
|
/* Register space */ |
`define ETH_MODER `ETH_BASE + 32'h00 /* Mode Register */ |
`define ETH_INT `ETH_BASE + 32'h04 /* Interrupt Source Register */ |
`define ETH_INT_MASK `ETH_BASE + 32'h08 /* Interrupt Mask Register */ |
`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */ |
`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */ |
`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */ |
`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */ |
`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */ |
`define ETH_RX_BD_NUM `ETH_BASE + 32'h20 /* Receive Buffer Descriptor Number Register */ |
`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */ |
`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */ |
`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */ |
`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */ |
`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */ |
`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */ |
`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */ |
`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */ |
`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */ |
`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */ |
`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */ |
|
/* MODER Register */ |
`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */ |
`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */ |
`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */ |
`define ETH_MODER_BRO 32'h00000008 /* Reject Broadcast */ |
`define ETH_MODER_IAM 32'h00000010 /* Use Individual Hash */ |
`define ETH_MODER_PRO 32'h00000020 /* Promiscuous (receive all) */ |
`define ETH_MODER_IFG 32'h00000040 /* Min. IFG not required */ |
`define ETH_MODER_LOOPBCK 32'h00000080 /* Loop Back */ |
`define ETH_MODER_NOBCKOF 32'h00000100 /* No Backoff */ |
`define ETH_MODER_EXDFREN 32'h00000200 /* Excess Defer */ |
`define ETH_MODER_FULLD 32'h00000400 /* Full Duplex */ |
`define ETH_MODER_RST 32'h00000800 /* Reset MAC */ |
`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */ |
`define ETH_MODER_CRCEN 32'h00002000 /* CRC Enable */ |
`define ETH_MODER_HUGEN 32'h00004000 /* Huge Enable */ |
`define ETH_MODER_PAD 32'h00008000 /* Pad Enable */ |
`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */ |
|
/* Interrupt Source Register */ |
`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */ |
`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */ |
`define ETH_INT_RXF 32'h00000004 /* Receive Frame IRQ */ |
`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */ |
`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */ |
`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */ |
`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */ |
|
/* Interrupt Mask Register */ |
`define ETH_INT_MASK_TXB 32'h00000001 /* Transmit Buffer IRQ Mask */ |
`define ETH_INT_MASK_TXE 32'h00000002 /* Transmit Error IRQ Mask */ |
`define ETH_INT_MASK_RXF 32'h00000004 /* Receive Frame IRQ Mask */ |
`define ETH_INT_MASK_RXE 32'h00000008 /* Receive Error IRQ Mask */ |
`define ETH_INT_MASK_BUSY 32'h00000010 /* Busy IRQ Mask */ |
`define ETH_INT_MASK_TXC 32'h00000020 /* Transmit Control Frame IRQ Mask */ |
`define ETH_INT_MASK_RXC 32'h00000040 /* Received Control Frame IRQ Mask */ |
|
/* Control Module Mode Register */ |
`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */ |
`define ETH_CTRLMODER_RXFLOW 32'h00000002 /* Receive Control Flow Enable */ |
`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */ |
|
/* MII Mode Register */ |
`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */ |
`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */ |
`define ETH_MIIMODER_RST 32'h00000200 /* MIIM Reset */ |
|
/* MII Command Register */ |
`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */ |
`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */ |
`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */ |
|
/* MII Address Register */ |
`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */ |
`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */ |
|
/* MII Status Register */ |
`define ETH_MIISTATUS_LINKFAIL 32'h00000001 /* Link Fail */ |
`define ETH_MIISTATUS_BUSY 32'h00000002 /* MII Busy */ |
`define ETH_MIISTATUS_NVALID 32'h00000004 /* Data in MII Status Register is invalid */ |