URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 118 to Rev 117
- ↔ Reverse comparison
Rev 118 → Rev 117
/trunk/rtl/verilog/eth_wishbone.v
13,7 → 13,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.28 2002/07/18 16:11:46 mohor |
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. |
// |
// Revision 1.27 2002/07/11 02:53:20 mohor |
// RxPointer bug fixed. |
// |
835,7 → 832,7
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
reg cyc_cleared; |
|
|
// Enabling master wishbone access to the memory for two devices TX and RX. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
1631,10 → 1628,6
reg ShiftEnded_tck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
|
wire StartShiftWillEnd; |
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow; |
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow; |
1842,7 → 1835,7
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i), |
.clear(RxFifoReset), .full(RxBufferFull), |
.almost_full(), .almost_empty(RxBufferAlmostEmpty), |
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty), |
.empty(RxBufferEmpty), .cnt() |
); |
|
1856,10 → 1849,10
if(Reset) |
ShiftEnded_tck <=#Tp 1'b0; |
else |
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) |
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck) |
ShiftEnded_tck <=#Tp 1'b1; |
else |
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) |
if(ShiftEnded | RxAbort) |
ShiftEnded_tck <=#Tp 1'b0; |
end |
|
1879,17 → 1872,6
ShiftEndedSync2 <=#Tp ShiftEndedSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync3 <=#Tp 1'b0; |
else |
if(ShiftEndedSync1 & ~ShiftEndedSync2) |
ShiftEndedSync3 <=#Tp 1'b1; |
else |
if(ShiftEnded) |
ShiftEndedSync3 <=#Tp 1'b0; |
end |
|
// Generation of the end-of-frame signal |
always @ (posedge WB_CLK_I or posedge Reset) |
1897,7 → 1879,7
if(Reset) |
ShiftEnded <=#Tp 1'b0; |
else |
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
ShiftEnded <=#Tp 1'b1; |
else |
if(RxStatusWrite) |
1904,22 → 1886,7
ShiftEnded <=#Tp 1'b0; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c1 <=#Tp 1'b0; |
else |
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c2 <=#Tp 1'b0; |
else |
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1; |
end |
|
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |