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  • This comparison shows the changes necessary to convert path
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    from Rev 126 to Rev 127
    Reverse comparison

Rev 126 → Rev 127

/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
934,6 → 937,13
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
end
6'b10_00_0_1, 6'b01_00_0_1 :
begin
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_stb_o <=#Tp 1'b0;
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
1849,7 → 1859,7
.empty(RxBufferEmpty), .cnt()
);
 
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
 
 
 

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