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https://opencores.org/ocsvn/ethmac/ethmac/trunk
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- from Rev 132 to Rev 131
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Rev 132 → Rev 131
/trunk/rtl/verilog/eth_registers.v
41,10 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2002/04/22 14:03:44 mohor |
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled |
// or not. |
// |
// Revision 1.13 2002/02/26 16:18:09 mohor |
// Reset values are passed to registers through parameters |
// |
328,16 → 324,27
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reg LinkFailRegister; |
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read; |
reg ResetLinkFailRegister_q1; |
reg ResetLinkFailRegister_q2; |
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always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
LinkFailRegister <= #Tp 0; |
begin |
LinkFailRegister <= #Tp 0; |
ResetLinkFailRegister_q1 <= #Tp 0; |
ResetLinkFailRegister_q2 <= #Tp 0; |
end |
else |
if(LinkFail) |
LinkFailRegister <= #Tp 1; |
else |
LinkFailRegister <= #Tp 0; |
begin |
ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister; |
ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1; |
if(LinkFail) |
LinkFailRegister <= #Tp 1; |
if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2) |
LinkFailRegister <= #Tp 0; |
end |
end |
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