URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
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- from Rev 160 to Rev 159
- ↔ Reverse comparison
Rev 160 → Rev 159
/trunk/rtl/verilog/eth_cop.v
41,19 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/08/14 17:16:07 mohor |
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave |
// interfaces: |
// - Host connects to the master interface |
// - Ethernet master (DMA) connects to the second master interface |
// - Memory interface connects to the slave interface |
// - Ethernet slave interface (access to registers and BDs) connects to second |
// slave interface |
// |
// |
// |
// |
// |
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`include "tb_eth_defines.v" |
`include "timescale.v" |
345,7 → 336,7
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); |
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o); |
end |
else if(s2_wb_cyc_o) begin |
else if(s1_wb_cyc_o) begin |
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); |
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); |
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); |
357,26 → 348,5
end |
|
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always @ (posedge wb_clk_i) |
begin |
if(s1_wb_err_i & s1_wb_cyc_o) begin |
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); |
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); |
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); |
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); |
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o); |
$stop; |
end |
if(s2_wb_err_i & s2_wb_cyc_o) begin |
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); |
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); |
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); |
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); |
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o); |
$stop; |
end |
end |
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endmodule |