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  • This comparison shows the changes necessary to convert path
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    from Rev 177 to Rev 176
    Reverse comparison

Rev 177 → Rev 176

/trunk/bench/verilog/eth_phy.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/13 12:29:14 mohor
// Headers changed.
//
// Revision 1.1 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
414,9 → 411,8
end
else // with preamble
begin
#4 ;
`ifdef VERBOSE
$fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time);
#4 $fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time);
`endif
if (md_io_reg !== 1'b0)
begin
/trunk/bench/verilog/tb_ethernet.v
42,9 → 42,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/09/13 12:29:14 mohor
// Headers changed.
//
// Revision 1.6 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
388,9 → 385,8
 
// Call tests
// ----------
// test_access_to_mac_reg(0, 3); // 0 - 3
// test_mii(0, 17); // 0 - 17
test_mii(0, 1); // 0 - 17
test_access_to_mac_reg(0, 3); // 0 - 3
test_mii(0, 17); // 0 - 17
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
eth_phy.carrier_sense_real_delay(0);
test_mac_full_duplex_transmit(0, 3); // 0 - (3)

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