URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- from Rev 204 to Rev 203
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Rev 204 → Rev 203
/trunk/rtl/verilog/eth_spram_256x32.v
8,7 → 8,7
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
41,15 → 41,12
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/07/23 16:36:09 mohor |
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used. |
// |
// |
// |
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`include "eth_defines.v" |
`include "timescale.v" |
|
|
module eth_spram_256x32( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
92,21 → 89,8
.RST (rst) |
); |
|
`else // !ETH_XILINX_RAMB4 |
`ifdef ETH_VIRTUAL_SILICON_RAM |
vs_hdsp_256x32 ram0 |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (!we), |
.OEN (!oe), |
.ADR (addr), |
.DI (di), |
.DOUT (do) |
); |
`else |
|
`else // !ETH_VIRTUAL_SILICON_RAM |
|
// |
// Generic single-port synchronous RAM model |
// |
150,7 → 134,6
end |
endtask |
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`endif // !ETH_VIRTUAL_SILICON_RAM |
`endif // !ETH_XILINX_RAMB4 |
`endif |
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endmodule |