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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
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    from Rev 241 to Rev 240
    Reverse comparison

Rev 241 → Rev 240

/trunk/rtl/verilog/eth_rxstatem.v
43,9 → 43,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
125,15 → 122,16
 
 
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData) & (ByteCntEq0 | ByteCntGreat2));
 
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
 
//assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
 
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
 
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartData1 = MRxDV & StateData0;
 
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame

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