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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 249 to Rev 250
    Reverse comparison

Rev 249 → Rev 250

/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
89,7 → 92,7
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss
);
 
parameter Tp = 1;
124,6 → 127,7
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
 
reg [7:0] RxData;
reg RxValid;
199,7 → 203,7
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm)
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss)
);
 
 
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
235,7 → 239,7
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
299,6 → 303,7
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
 
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
463,8 → 468,8
 
reg WB_ACK_O;
 
wire [6:0] RxStatusIn;
reg [6:0] RxStatusInLatched;
wire [7:0] RxStatusIn;
reg [7:0] RxStatusInLatched;
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
1343,7 → 1348,7
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
2359,7 → 2364,7
end
 
 
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
always @ (posedge MRxClk or posedge Reset)
begin
2392,7 → 2397,9
wire RxError;
 
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
 
// Tx Done Interrupt
/trunk/rtl/verilog/eth_rxaddrcheck.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
64,7 → 67,7
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort
Multicast, MAC, RxAbort, AddressMiss
);
 
parameter Tp = 1;
91,8 → 94,8
input RxEndFrm;
output RxAbort;
output AddressMiss;
 
 
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
106,6 → 109,7
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
126,9 → 130,18
RxAbort <= #Tp 1'b0;
end
// Hash Address Check, Multicast
 
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK));
end
 
 
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.39 2002/11/18 17:31:55 mohor
// wb_rst_i is used for MIIM reset.
//
// Revision 1.38 2002/11/14 18:37:20 mohor
// r_Rst signal does not reset any module any more and is removed from the design.
//
589,10 → 592,10
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
 
 
 
 
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
605,7 → 608,8
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort)
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss)
);
 
 
771,7 → 775,7
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss)
`ifdef ETH_BIST
,

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