URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 255 to Rev 254
- ↔ Reverse comparison
Rev 255 → Rev 254
/trunk/rtl/verilog/eth_top.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.41 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.40 2002/11/19 17:34:25 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
342,12 → 339,7
reg WillSendControlFrame_sync3; |
reg RstTxPauseRq; |
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reg TxPauseRq_sync1; |
reg TxPauseRq_sync2; |
reg TxPauseRq_sync3; |
reg TPauseRq; |
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// Connecting Miim module |
eth_miim miim1 |
( |
523,7 → 515,7
// Connecting MACControl |
eth_maccontrol maccontrol1 |
( |
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq), |
.MTxClk(mtx_clk_pad_i), .TPauseRq(r_TxPauseRq), |
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData), |
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm), |
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn), |
741,37 → 733,6
end |
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// TX Pause request Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
TxPauseRq_sync1 <= #Tp 1'b0; |
TxPauseRq_sync2 <= #Tp 1'b0; |
TxPauseRq_sync3 <= #Tp 1'b0; |
end |
else |
begin |
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow); |
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1; |
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2; |
end |
end |
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always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
TPauseRq <= #Tp 1'b0; |
else |
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3); |
end |
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// Connecting Wishbone module |
eth_wishbone wishbone |
( |