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    from Rev 264 to Rev 263
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Rev 264 → Rev 263

/trunk/rtl/verilog/eth_wishbone.v
41,10 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
1809,6 → 1805,7
reg RxAbortSyncb1;
reg RxAbortSyncb2;
 
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
 
// Reading the Rx buffer descriptor
1941,6 → 1938,34
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
reg RxStatusWriteLatched;
reg RxStatusWrite_rck;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite & ~RxStatusWrite_rck)
RxStatusWriteLatched <=#Tp 1'b1;
else
if(RxStatusWrite_rck)
RxStatusWriteLatched <=#Tp 1'b0;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusWrite_rck <=#Tp 1'b0;
else
if(RxStatusWriteLatched)
RxStatusWrite_rck <=#Tp 1'b1;
else
RxStatusWrite_rck <=#Tp 1'b0;
end
 
 
reg RxEnableWindow;
 
// Indicating that last byte is being reveived

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