OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 275 to Rev 276
    Reverse comparison

Rev 275 → Rev 276

/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.45 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.44 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
601,7 → 604,7
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.StartDefer(StartDefer), .StatePreamble(StatePreamble), .StateData(StateData)
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
 
 
910,7 → 913,7
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .StartDefer(StartDefer), .DeferLatched(DeferLatched),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13 2002/11/13 22:30:58 tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
109,7 → 113,7
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
147,7 → 151,7
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input StartDefer;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
389,7 → 393,7
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(StartDefer & TxUsedData)
if(DeferIndication & TxUsedData)
DeferLatched <=#Tp 1'b1;
else
if(TxStartFrm)
/trunk/rtl/verilog/eth_txstatem.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/10/30 12:54:50 mohor
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
90,7 → 93,7
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, StartPreamble, StartData, StartIPG
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
 
parameter Tp = 1;
139,6 → 142,7
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
186,8 → 190,8
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
 
assign DeferIndication = StateIdle & CarrierSense;
 
 
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin

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