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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 296 to Rev 297
    Reverse comparison

Rev 296 → Rev 297

/trunk/rtl/verilog/eth_spram_256x32.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
148,6 → 151,33
 
`else // !ETH_VIRTUAL_SILICON_RAM
 
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
art_hssp_256x32_bist ram0_bist
`else
art_hssp_256x32 ram0
`endif
(
.CLK (clk),
.CEN (!ce),
.WEN (!we),
.OEN (!oe),
.A (addr),
.D (di),
.Q (do)
 
`ifdef ETH_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
 
`else // !ETH_ARTISAN_RAM
//
// Generic single-port synchronous RAM model
//
191,6 → 221,7
end
endtask
 
`endif // !ETH_ARTISAN_RAM
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
 
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.30 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
173,6 → 177,7
 
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
 
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4

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