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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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    from Rev 303 to Rev 304
    Reverse comparison

Rev 303 → Rev 304

/trunk/rtl/verilog/eth_spram_256x32.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/10/17 07:46:15 markom
// mbist signals updated according to newest convention
//
// Revision 1.5 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
84,7 → 87,7
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input we; // Write enable input, active high
input [3:0] we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
99,7 → 102,7
 
`ifdef ETH_XILINX_RAMB4
 
RAMB4_S16 ram0
/*RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
119,14 → 122,60
.CLK (clk),
.WE (we),
.RST (rst)
);*/
 
RAMB4_S8 ram0
(
.DO (do[7:0]),
.ADDR (addr),
.DI (di[7:0]),
.EN (ce),
.CLK (clk),
.WE (we[0]),
.RST (rst)
);
 
RAMB4_S8 ram1
(
.DO (do[15:8]),
.ADDR (addr),
.DI (di[15:8]),
.EN (ce),
.CLK (clk),
.WE (we[1]),
.RST (rst)
);
 
RAMB4_S8 ram2
(
.DO (do[23:16]),
.ADDR (addr),
.DI (di[23:16]),
.EN (ce),
.CLK (clk),
.WE (we[2]),
.RST (rst)
);
 
RAMB4_S8 ram3
(
.DO (do[31:24]),
.ADDR (addr),
.DI (di[31:24]),
.EN (ce),
.CLK (clk),
.WE (we[3]),
.RST (rst)
);
 
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
vs_hdsp_256x32_bist ram0_bist
//vs_hdsp_256x32_bist ram0_bist
vs_hdsp_256x32_bw_bist ram0_bist
`else
vs_hdsp_256x32 ram0
//vs_hdsp_256x32 ram0
vs_hdsp_256x32_bw ram0
`endif
(
.CK (clk),
150,9 → 199,11
 
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
art_hssp_256x32_bist ram0_bist
//art_hssp_256x32_bist ram0_bist
art_hssp_256x32_bw_bist ram0_bist
`else
art_hssp_256x32 ram0
//art_hssp_256x32 ram0
art_hssp_256x32_bw ram0
`endif
(
.CLK (clk),
180,9 → 231,12
//
// Generic RAM's registers and wires
//
reg [31:0] mem [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
reg [ 7: 0] mem0 [255:0]; // RAM content
reg [15: 8] mem1 [255:0]; // RAM content
reg [23:16] mem2 [255:0]; // RAM content
reg [31:24] mem3 [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
194,15 → 248,23
 
// read operation
always@(posedge clk)
if (ce) // && !we)
if (ce) // && !we)
raddr <= #1 addr; // read address needs to be registered to read clock
 
assign #1 q = rst ? {32{1'b0}} : mem[raddr];
assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
 
// write operation
always@(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
begin
if (ce && we[3])
mem3[addr] <= #1 di[31:24];
if (ce && we[2])
mem2[addr] <= #1 di[23:16];
if (ce && we[1])
mem1[addr] <= #1 di[15: 8];
if (ce && we[0])
mem0[addr] <= #1 di[ 7: 0];
end
 
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
212,7 → 274,7
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %h",rnum,mem[rnum]);
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
 
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.32 2003/10/17 07:46:13 markom
// mbist signals updated according to newest convention
//
// Revision 1.31 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
207,48 → 210,93
`define ETH_RX_CTRL_ADR 8'h15 // 0x54
 
 
`define ETH_MODER_DEF 17'h0A000
`define ETH_INT_MASK_DEF 7'h0
`define ETH_IPGT_DEF 7'h12
`define ETH_IPGR1_DEF 7'h0C
`define ETH_IPGR2_DEF 7'h12
`define ETH_PACKETLEN_DEF 32'h00400600
`define ETH_COLLCONF0_DEF 6'h3f
`define ETH_COLLCONF1_DEF 4'hF
`define ETH_TX_BD_NUM_DEF 8'h40
`define ETH_CTRLMODER_DEF 3'h0
`define ETH_MIIMODER_DEF 10'h064
`define ETH_MIIADDRESS0_DEF 5'h00
`define ETH_MIIADDRESS1_DEF 5'h00
`define ETH_MIITX_DATA_DEF 16'h0000
`define ETH_MIIRX_DATA_DEF 16'h0000
`define ETH_MIISTATUS_DEF 32'h00000000
`define ETH_MAC_ADDR0_DEF 32'h00000000
`define ETH_MAC_ADDR1_DEF 16'h0000
`define ETH_HASH0_DEF 32'h00000000
`define ETH_HASH1_DEF 32'h00000000
`define ETH_RX_CTRL_DEF 16'h0
`define ETH_MODER_DEF_0 8'h00
`define ETH_MODER_DEF_1 8'hA0
`define ETH_MODER_DEF_2 1'h0
`define ETH_INT_MASK_DEF_0 7'h0
`define ETH_IPGT_DEF_0 7'h12
`define ETH_IPGR1_DEF_0 7'h0C
`define ETH_IPGR2_DEF_0 7'h12
`define ETH_PACKETLEN_DEF_0 8'h00
`define ETH_PACKETLEN_DEF_1 8'h06
`define ETH_PACKETLEN_DEF_2 8'h40
`define ETH_PACKETLEN_DEF_3 8'h00
`define ETH_COLLCONF_DEF_0 6'h3f
`define ETH_COLLCONF_DEF_2 4'hF
`define ETH_TX_BD_NUM_DEF_0 8'h40
`define ETH_CTRLMODER_DEF_0 3'h0
`define ETH_MIIMODER_DEF_0 8'h64
`define ETH_MIIMODER_DEF_1 1'h0
`define ETH_MIIADDRESS_DEF_0 5'h00
`define ETH_MIIADDRESS_DEF_1 5'h00
`define ETH_MIITX_DATA_DEF_0 8'h00
`define ETH_MIITX_DATA_DEF_1 8'h00
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
`define ETH_MAC_ADDR0_DEF_0 8'h00
`define ETH_MAC_ADDR0_DEF_1 8'h00
`define ETH_MAC_ADDR0_DEF_2 8'h00
`define ETH_MAC_ADDR0_DEF_3 8'h00
`define ETH_MAC_ADDR1_DEF_0 8'h00
`define ETH_MAC_ADDR1_DEF_1 8'h00
`define ETH_HASH0_DEF_0 8'h00
`define ETH_HASH0_DEF_1 8'h00
`define ETH_HASH0_DEF_2 8'h00
`define ETH_HASH0_DEF_3 8'h00
`define ETH_HASH1_DEF_0 8'h00
`define ETH_HASH1_DEF_1 8'h00
`define ETH_HASH1_DEF_2 8'h00
`define ETH_HASH1_DEF_3 8'h00
`define ETH_TX_CTRL_DEF_0 8'h00 //
`define ETH_TX_CTRL_DEF_1 8'h00 //
`define ETH_TX_CTRL_DEF_2 1'h0 //
`define ETH_RX_CTRL_DEF_0 8'h00
`define ETH_RX_CTRL_DEF_1 8'h00
 
 
`define ETH_MODER_WIDTH 17
`define ETH_INT_SOURCE_WIDTH 7
`define ETH_INT_MASK_WIDTH 7
`define ETH_IPGT_WIDTH 7
`define ETH_IPGR1_WIDTH 7
`define ETH_IPGR2_WIDTH 7
`define ETH_PACKETLEN_WIDTH 32
`define ETH_TX_BD_NUM_WIDTH 8
`define ETH_CTRLMODER_WIDTH 3
`define ETH_MIIMODER_WIDTH 9
`define ETH_MIITX_DATA_WIDTH 16
`define ETH_MIIRX_DATA_WIDTH 16
`define ETH_MIISTATUS_WIDTH 3
`define ETH_MAC_ADDR0_WIDTH 32
`define ETH_MAC_ADDR1_WIDTH 16
`define ETH_HASH0_WIDTH 32
`define ETH_HASH1_WIDTH 32
`define ETH_TX_CTRL_WIDTH 17
`define ETH_RX_CTRL_WIDTH 16
`define ETH_MODER_WIDTH_0 8
`define ETH_MODER_WIDTH_1 8
`define ETH_MODER_WIDTH_2 1
`define ETH_INT_SOURCE_WIDTH_0 7
`define ETH_INT_MASK_WIDTH_0 7
`define ETH_IPGT_WIDTH_0 7
`define ETH_IPGR1_WIDTH_0 7
`define ETH_IPGR2_WIDTH_0 7
`define ETH_PACKETLEN_WIDTH_0 8
`define ETH_PACKETLEN_WIDTH_1 8
`define ETH_PACKETLEN_WIDTH_2 8
`define ETH_PACKETLEN_WIDTH_3 8
`define ETH_COLLCONF_WIDTH_0 6
`define ETH_COLLCONF_WIDTH_2 4
`define ETH_TX_BD_NUM_WIDTH_0 8
`define ETH_CTRLMODER_WIDTH_0 3
`define ETH_MIIMODER_WIDTH_0 8
`define ETH_MIIMODER_WIDTH_1 1
`define ETH_MIICOMMAND_WIDTH_0 3
`define ETH_MIIADDRESS_WIDTH_0 5
`define ETH_MIIADDRESS_WIDTH_1 5
`define ETH_MIITX_DATA_WIDTH_0 8
`define ETH_MIITX_DATA_WIDTH_1 8
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
`define ETH_MIISTATUS_WIDTH 3 // not written from WB
`define ETH_MAC_ADDR0_WIDTH_0 8
`define ETH_MAC_ADDR0_WIDTH_1 8
`define ETH_MAC_ADDR0_WIDTH_2 8
`define ETH_MAC_ADDR0_WIDTH_3 8
`define ETH_MAC_ADDR1_WIDTH_0 8
`define ETH_MAC_ADDR1_WIDTH_1 8
`define ETH_HASH0_WIDTH_0 8
`define ETH_HASH0_WIDTH_1 8
`define ETH_HASH0_WIDTH_2 8
`define ETH_HASH0_WIDTH_3 8
`define ETH_HASH1_WIDTH_0 8
`define ETH_HASH1_WIDTH_1 8
`define ETH_HASH1_WIDTH_2 8
`define ETH_HASH1_WIDTH_3 8
`define ETH_TX_CTRL_WIDTH_0 8
`define ETH_TX_CTRL_WIDTH_1 8
`define ETH_TX_CTRL_WIDTH_2 1
`define ETH_RX_CTRL_WIDTH_0 8
`define ETH_RX_CTRL_WIDTH_1 8
 
 
// Outputs are registered (uncomment when needed)
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
299,7 → 302,7
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input BDCs; // Buffer descriptors are selected
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
 
// WISHBONE master
466,7 → 469,7
reg ShiftEnded;
reg RxOverrun;
 
reg BDWrite; // BD Write Enable for access from WISHBONE side
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
504,7 → 507,7
reg TxEn, TxEn_q;
 
wire ram_ce;
wire ram_we;
wire [3:0] ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
525,7 → 528,7
 
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
 
assign WB_DAT_O = ram_do;
542,7 → 545,7
);
 
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
 
 
598,8 → 601,8
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
616,8 → 619,8
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
630,8 → 633,8
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
endcase
end
1347,10 → 1350,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
else
if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
RxBDAddress <=#Tp WB_DAT_I[7:0] << 1;
else
if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.48 2003/10/17 07:46:16 markom
// mbist signals updated according to newest convention
//
// Revision 1.47 2003/10/06 15:43:45 knguyen
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
//
379,7 → 382,7
 
 
 
wire RegCs; // Connected to registers
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
423,10 → 426,12
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
 
wire DWord;
//wire DWord;
wire ByteSelected;
wire [3:0] ByteSel;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire BDCs; // Buffer descriptor CS
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
 
440,13 → 445,20
reg temp_wb_err_o_reg;
`endif
 
assign DWord = &wb_sel_i;
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_ack_o = RegCs | BDAck;
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_ack_o = (|RegCs) | BDAck;
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
 
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25 2003/04/18 16:26:25 mohor
// RxBDAddress was updated also when value to r_TxBDNum was written with
// greater value than allowed.
//
// Revision 1.24 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
169,7 → 173,7
input [7:0] Address;
 
input Rw;
input Cs;
input [3:0] Cs;
input Clk;
input Reset;
 
273,31 → 277,31
reg ResetRxCIrq_sync2;
reg ResetRxCIrq_sync3;
 
wire Write = Cs & Rw;
wire Read = Cs & ~Rw;
wire [3:0] Write = Cs & {4{Rw}};
wire Read = (|Cs) & ~Rw;
 
wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
wire MODER_Wr = (Address == `ETH_MODER_ADR );
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR );
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR );
wire IPGT_Wr = (Address == `ETH_IPGT_ADR );
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR );
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR );
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR );
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR );
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR );
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR );
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR );
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR );
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR );
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write & (DataIn<='h80);
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR );
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR );
wire HASH0_Wr = (Address == `ETH_HASH0_ADR );
wire HASH1_Wr = (Address == `ETH_HASH1_ADR );
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR );
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR );
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & (DataIn<='h80);
 
 
 
325,134 → 329,187
wire [31:0] RXCTRLOut;
 
// MODER Register
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
(
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
.Write (MODER_Wr),
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
.Write (MODER_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
(
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
.Write (MODER_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
(
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
.Write (MODER_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
 
// INT_MASK Register
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
(
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
.Write (INT_MASK_Wr),
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.Write (INT_MASK_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
 
// IPGT Register
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
(
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
.Write (IPGT_Wr),
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
.Write (IPGT_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
 
// IPGR1 Register
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
(
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
.Write (IPGR1_Wr),
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
.Write (IPGR1_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
 
// IPGR2 Register
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
(
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
.Write (IPGR2_Wr),
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
.Write (IPGR2_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
 
// PACKETLEN Register
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
(
.DataIn (DataIn),
.DataOut (PACKETLENOut),
.Write (PACKETLEN_Wr),
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.Write (PACKETLEN_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.Write (PACKETLEN_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.Write (PACKETLEN_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.Write (PACKETLEN_Wr & Write[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
// COLLCONF Register
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
(
.DataIn (DataIn[5:0]),
.DataOut (COLLCONFOut[5:0]),
.Write (COLLCONF_Wr),
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.Write (COLLCONF_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[15:6] = 0;
 
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
(
.DataIn (DataIn[19:16]),
.DataOut (COLLCONFOut[19:16]),
.Write (COLLCONF_Wr),
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.Write (COLLCONF_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[31:20] = 0;
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
 
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
.Write (TX_BD_NUM_Wr),
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.Write (TX_BD_NUM_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
 
// CTRLMODER Register
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
(
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
.Write (CTRLMODER_Wr),
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.Write (CTRLMODER_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
 
// MIIMODER Register
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
.Write (MIIMODER_Wr),
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.Write (MIIMODER_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.Write (MIIMODER_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
 
// MIICOMMAND Register
eth_register #(1, 0) MIICOMMAND0
459,67 → 516,73
(
.DataIn (DataIn[0]),
.DataOut (MIICOMMANDOut[0]),
.Write (MIICOMMAND_Wr),
.Write (MIICOMMAND_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
eth_register #(1, 0) MIICOMMAND1
(
.DataIn (DataIn[1]),
.DataOut (MIICOMMANDOut[1]),
.Write (MIICOMMAND_Wr),
.Write (MIICOMMAND_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RStatStart)
);
 
eth_register #(1, 0) MIICOMMAND2
(
.DataIn (DataIn[2]),
.DataOut (MIICOMMANDOut[2]),
.Write (MIICOMMAND_Wr),
.Write (MIICOMMAND_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (WCtrlDataStart)
);
assign MIICOMMANDOut[31:3] = 29'h0;
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
 
// MIIADDRESSRegister
eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
(
.DataIn (DataIn[4:0]),
.DataOut (MIIADDRESSOut[4:0]),
.Write (MIIADDRESS_Wr),
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.Write (MIIADDRESS_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[7:5] = 0;
 
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
(
.DataIn (DataIn[12:8]),
.DataOut (MIIADDRESSOut[12:8]),
.Write (MIIADDRESS_Wr),
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.Write (MIIADDRESS_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[31:13] = 0;
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
 
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
.Write (MIITX_DATA_Wr),
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.Write (MIITX_DATA_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.Write (MIITX_DATA_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
 
// MIIRX_DATA Register
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
526,7 → 589,7
(
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
.Write (MIIRX_DATA_Wr),
.Write (MIIRX_DATA_Wr), // not written from WB
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
534,85 → 597,190
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
 
// MAC_ADDR0 Register
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
(
.DataIn (DataIn),
.DataOut (MAC_ADDR0Out),
.Write (MAC_ADDR0_Wr),
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.Write (MAC_ADDR0_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.Write (MAC_ADDR0_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.Write (MAC_ADDR0_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.Write (MAC_ADDR0_Wr & Write[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
// MAC_ADDR1 Register
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
.Write (MAC_ADDR1_Wr),
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.Write (MAC_ADDR1_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.Write (MAC_ADDR1_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
 
// RXHASH0 Register
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
(
.DataIn (DataIn),
.DataOut (HASH0Out),
.Write (HASH0_Wr),
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
.Write (HASH0_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
.Write (HASH0_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
.Write (HASH0_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
.Write (HASH0_Wr & Write[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
// RXHASH1 Register
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
(
.DataIn (DataIn),
.DataOut (HASH1Out),
.Write (HASH1_Wr),
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
.Write (HASH1_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
.Write (HASH1_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
.Write (HASH1_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
.Write (HASH1_Wr & Write[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
 
// TXCTRL Register
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}}) TXCTRL0
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
.Write (TXCTRL_Wr),
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.Write (TXCTRL_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
 
eth_register #(1, 1'b0) TXCTRL1 // Request bit is synchronously reset
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
(
.DataIn (DataIn[16]),
.DataOut (TXCTRLOut[16]),
.Write (TXCTRL_Wr),
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.Write (TXCTRL_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.Write (TXCTRL_Wr & Write[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RstTxPauseRq)
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
 
 
// RXCTRL Register
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF) RXCTRL
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0) RXCTRL_0
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
.Write (RXCTRL_Wr),
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
.Write (RXCTRL_Wr & Write[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1) RXCTRL_1
(
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
.Write (RXCTRL_Wr & Write[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
 
 
// Reading data from registers
864,7 → 1032,7
if(TxB_IRQ)
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[0])
if(INT_SOURCE_Wr & Write[0] & DataIn[0])
irq_txb <= #Tp 1'b0;
end
 
876,7 → 1044,7
if(TxE_IRQ)
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[1])
if(INT_SOURCE_Wr & Write[0] & DataIn[1])
irq_txe <= #Tp 1'b0;
end
 
888,7 → 1056,7
if(RxB_IRQ)
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[2])
if(INT_SOURCE_Wr & Write[0] & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
 
900,7 → 1068,7
if(RxE_IRQ)
irq_rxe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[3])
if(INT_SOURCE_Wr & Write[0] & DataIn[3])
irq_rxe <= #Tp 1'b0;
end
 
912,7 → 1080,7
if(Busy_IRQ)
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[4])
if(INT_SOURCE_Wr & Write[0] & DataIn[4])
irq_busy <= #Tp 1'b0;
end
 
924,7 → 1092,7
if(SetTxCIrq)
irq_txc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[5])
if(INT_SOURCE_Wr & Write[0] & DataIn[5])
irq_txc <= #Tp 1'b0;
end
 
936,7 → 1104,7
if(SetRxCIrq)
irq_rxc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[6])
if(INT_SOURCE_Wr & Write[0] & DataIn[6])
irq_rxc <= #Tp 1'b0;
end
 
950,7 → 1118,7
irq_rxc & INT_MASKOut[6] ;
 
// For reading interrupt status
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
 
 
 

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