URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 32 to Rev 31
- ↔ Reverse comparison
Rev 32 → Rev 31
/trunk/rtl/verilog/eth_defines.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
72,10 → 69,6
// |
// |
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//`define WISHBONE_DMA // Using DMA |
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// Selection of the used memory |
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex |
// specific elements. |
91,7 → 84,7
`define ETH_IPGR2_ADR 6'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 6'h6 // 0x18 |
`define ETH_COLLCONF_ADR 6'h7 // 0x1C |
`define ETH_RX_BD_NUM_ADR 6'h8 // 0x20 |
`define ETH_RX_BD_ADR_ADR 6'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 6'h9 // 0x24 |
`define ETH_MIIMODER_ADR 6'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C |
122,4 → 115,4
`define ETH_MAC_ADDR0_DEF 32'h00000000 |
`define ETH_MAC_ADDR1_DEF 32'h00000000 |
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`define ETH_RX_BD_NUM_DEF 8'h80 |
`define ETH_RX_BD_ADR_DEF 8'h0 |
/trunk/rtl/verilog/eth_registers.v
41,10 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
91,7 → 87,7
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_RxBDNum, RX_BD_NUM_Wr, int_o |
UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr, int_o |
); |
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parameter Tp = 1; |
173,8 → 169,8
input LinkFail; |
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output [47:0]r_MAC; |
output [7:0] r_RxBDNum; |
output RX_BD_NUM_Wr; |
output [7:0] r_RxBDAddress; |
output RX_BD_ADR_Wr; |
output int_o; |
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reg irq_txb; |
204,7 → 200,7
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write; |
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write; |
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write; |
assign RX_BD_NUM_Wr = (Address == `ETH_RX_BD_NUM_ADR ) & Write; |
assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR ) & Write; |
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225,7 → 221,7
wire [31:0] MIISTATUSOut; |
wire [31:0] MAC_ADDR0Out; |
wire [31:0] MAC_ADDR1Out; |
wire [31:0] RX_BD_NUMOut; |
wire [31:0] RX_BD_ADROut; |
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF)); |
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF)); |
259,8 → 255,8
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF)); |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF)); |
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assign RX_BD_NUMOut[31:8] = 24'h0; |
eth_register #(8) RX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(RX_BD_NUMOut[7:0]), .Write(RX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_NUM_DEF)); |
assign RX_BD_ADROut[31:8] = 24'h0; |
eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_ADR_DEF)); |
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reg LinkFailRegister; |
292,7 → 288,7
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or |
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or |
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or |
RX_BD_NUMOut) |
RX_BD_ADROut) |
begin |
if(Read) // read |
begin |
314,7 → 310,7
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; |
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
`ETH_RX_BD_NUM_ADR : DataOut<=RX_BD_NUMOut; |
`ETH_RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut; |
default: DataOut<=32'h0; |
endcase |
end |
382,7 → 378,7
assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |
assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; |
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assign r_RxBDNum[7:0] = RX_BD_NUMOut[7:0]; |
assign r_RxBDAddress[7:0] = RX_BD_ADROut[7:0]; |
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// Interrupt generation |