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  • This comparison shows the changes necessary to convert path 
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    from Rev 329 to Rev 330
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Rev 329 → Rev 330

/trunk/rtl/verilog/eth_spram_256x32.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/12/05 12:43:06 tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8 2003/12/04 14:59:13 simons
// Lapsus fixed (!we -> ~we).
//
225,11 → 228,25
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
`else // !ETH_ARTISAN_RAM
`ifdef ETH_ALTERA_ALTSYNCRAM
 
altera_spram_256x32 altera_spram_256x32_inst
(
.address (addr),
.wren (ce & we),
.clock (clk),
.data (di),
.q (do)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
`else // !ETH_ALTERA_ALTSYNCRAM
 
 
//
// Generic single-port synchronous RAM model
//
284,6 → 301,7
end
endtask
 
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_ARTISAN_RAM
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,14
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
152,7 → 160,6
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [3:0] LatchedNibble;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
179,8 → 186,8
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
 
 
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
 
204,7 → 211,7
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCnt(ByteCnt)
.ByteCntOut(ByteCnt)
);
 
// Rx Address Check
262,14 → 269,12
begin
RxData_d[7:0] <= #Tp 8'h0;
DelayData <= #Tp 1'b0;
LatchedNibble[3:0] <= #Tp 4'h0;
LatchedByte[7:0] <= #Tp 8'h0;
RxData[7:0] <= #Tp 8'h0;
end
else
begin
LatchedNibble[3:0] <= #Tp MRxD[3:0]; // Latched nibble
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedNibble[3:0]}; // Latched byte
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
DelayData <= #Tp StateData[0];
 
if(GenerateRxValid)
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.33 2003/11/12 18:24:58 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.32 2003/10/17 07:46:13 markom
// mbist signals updated according to newest convention
//
176,16 → 179,24
 
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
 
// Ethernet implemented in Xilinx Chips
// Ethernet implemented in Xilinx Chips (uncomment following lines)
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
// Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
 
// Ethernet implemented in Altera Chips (uncomment following lines)
//`define ETH_ALTERA_ALTSYNCRAM
 
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
 
// Ethernet implemented in ASIC with Artisan RAMs
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
 
// Uncomment when Avalon bus is used
//`define ETH_AVALON_BUS
 
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
/trunk/rtl/verilog/eth_fifo.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
79,7 → 83,11
 
`ifdef ETH_FIFO_XILINX
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
`ifdef ETH_ALTERA_ALTSYNCRAM
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
`endif
`endif
 
reg [CNT_WIDTH-1:0] cnt;
142,7 → 150,18
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst
(
.data (data_in),
.wren (write & ~full),
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
.clock (clk),
.q (data_out)
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
always @ (posedge clk)
begin
if(write & clear)
152,8 → 171,16
fifo[write_pointer] <=#Tp data_in;
end
assign data_out = clear ? fifo[0] : fifo[read_pointer];
`endif
 
always @ (posedge clk)
begin
if(clear)
data_out <=#Tp fifo[0];
else
data_out <=#Tp fifo[read_pointer];
end
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_FIFO_XILINX
 
 
endmodule
/trunk/rtl/verilog/eth_clockgen.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
86,7 → 89,7
 
 
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
 
 
// Counter counts half period
/trunk/rtl/verilog/eth_miim.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
174,8 → 177,8
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
 
 
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;

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