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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /ethmac/tags/rel_14/sim/rtl_sim
    from Rev 335 to Rev 338
    Reverse comparison

Rev 335 → Rev 338

/modelsim_sim/run/tb_eth.do
0,0 → 1,125
#/////////////////////////////////////////////////////////////////////
#/// ////
#/// tb_eth.do ////
#/// ////
#/// This file is part of the Ethernet IP core project ////
#/// http://www.opencores.org/projects/ethmac/ ////
#/// ////
#/// Author(s): ////
#/// - Igor Mohor (igorM@opencores.org) ////
#/// ////
#/// All additional information is avaliable in the Readme.txt ////
#/// file. ////
#/// ////
#/////////////////////////////////////////////////////////////////////
#/// ////
#/// Copyright (C) 2001, 2002 Authors ////
#/// ////
#/// This source file may be used and distributed without ////
#/// restriction provided that this copyright statement is not ////
#/// removed from the file and that any derivative work contains ////
#/// the original copyright notice and the associated disclaimer. ////
#/// ////
#/// This source file is free software; you can redistribute it ////
#/// and/or modify it under the terms of the GNU Lesser General ////
#/// Public License as published by the Free Software Foundation; ////
#/// either version 2.1 of the License, or (at your option) any ////
#/// later version. ////
#/// ////
#/// This source is distributed in the hope that it will be ////
#/// useful, but WITHOUT ANY WARRANTY; without even the implied ////
#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
#/// PURPOSE. See the GNU Lesser General Public License for more ////
#/// details. ////
#/// ////
#/// You should have received a copy of the GNU Lesser General ////
#/// Public License along with this source; if not, download it ////
#/// from http://www.opencores.org/lgpl.shtml ////
#/// ////
#/////////////////////////////////////////////////////////////////////
#/
#/ CVS Revision History
#/
#/ $Log: not supported by cvs2svn $
#/ Revision 1.4 2002/10/11 13:33:56 mohor
#/ Bist supported.
#/
#/ Revision 1.3 2002/10/11 12:42:12 mohor
#/ Bist supported.
#/
#/ Revision 1.2 2002/09/23 18:27:36 mohor
#/ ETH_VIRTUAL_SILICON_RAM supported.
#/
#/ Revision 1.1 2002/09/17 19:10:17 mohor
#/ Macro for testbench (DO file).
#/
#/
#/
#/
 
 
#write format wave -window .wave C:/Projects/ethernet/tadejm/ethernet/sim/rtl_sim/modelsim_sim/bin/wave.do
#.main clear
 
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_clockgen.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_crc.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_defines.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_fifo.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_maccontrol.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_macstatus.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_miim.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_outputcontrol.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_random.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_receivecontrol.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_register.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_registers.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxaddrcheck.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxcounters.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxethmac.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxstatem.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_shiftreg.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_spram_256x32.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_top.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_transmitcontrol.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txcounters.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txethmac.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txstatem.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_wishbone.v}
vlog -reportprogress 300 -work work {../../../../rtl/verilog/timescale.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy_defines.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_eth_defines.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_ethernet.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_bus_mon.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master_behavioral.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master32.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_model_defines.v}
vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_slave_behavioral.v}
 
 
# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/glbl.v}
# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/unisims/RAMB4_S16.v}
 
# If you use define ETH_VIRTUAL_SILICON_RAM switched on, then uncomment the following lines
# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32.v}
 
# If you use define ETH_VIRTUAL_SILICON_RAM and ETH_BIST switched on, then uncomment
# the following lines
# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist.v}
# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist_int.v}
# vlog -reportprogress 300 -work work {../../../../../jtag_marvin/jt_bc1in.v}
# vlog -reportprogress 300 -work work {../../../../../bist_marvin/bist.v}
 
# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
# !ETH_XILINX_RAMB4
vsim work.tb_ethernet
# ETH_XILINX_RAMB4
#vsim work.glbl work.tb_ethernet
 
 
do ../bin/eth_wave.do
#do ../bin/wave.do
run -all
 
/modelsim_sim/run/dir.keeper Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
modelsim_sim/run/dir.keeper Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: modelsim_sim/bin/eth_wave.do =================================================================== --- modelsim_sim/bin/eth_wave.do (nonexistent) +++ modelsim_sim/bin/eth_wave.do (revision 338) @@ -0,0 +1,138 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_clk +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_rst +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_int +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/mtx_clk +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/mrx_clk +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxD +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxEn +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxErr +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxD +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxDV +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxErr +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MColl +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MCrs +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdi_I +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdo_O +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdo_OE +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdio_IO +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdc_O +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_adr +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_adr_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_dat_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_dat_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_sel_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_we_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_cyc_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_stb_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_ack_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_err_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_adr_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_dat_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_dat_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_sel_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_we_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_cyc_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_stb_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_ack_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_err_i +add wave -noupdate -format Logic -radix ascii /tb_ethernet/test_name +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbm_init_waits +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbm_subseq_waits +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbs_waits +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbs_retries + +add wave -noupdate -format Logic -radix hex /tb_ethernet/eth_top/wishbone/* +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_receive/i_length +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_receive/num_of_bd +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/max_tmp +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/min_tmp +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/i_length +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/num_of_frames +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/num_of_bd +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_slave/calc_ack +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_slave/a_e_r_resp +add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/frame_ended + +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/m_rst_n_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtx_clk_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxd_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxen_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxerr_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrx_clk_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxd_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxdv_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxerr_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcoll_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_o +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mdc_i +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_log +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit15 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit14_10 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit9 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit8_0 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit15_9 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit8 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit7 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit6_0 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_id1 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_id2 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/rx_link_down_halfperiod +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/eth_speed +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/respond_to_all_phy_addr +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_preamble +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_transfer_cnt +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_transfer_cnt_reset +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_reg +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_output +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_rd_wr +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_enable +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_address +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_address +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_phy_address +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_reg_address +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_data_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_reg_data_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_put_reg_data_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_data_out +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_put_reg_data_out +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/register_bus_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/register_bus_out +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/registers_addr_data_test_operation +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d0 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d1 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d2 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d3 +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_rx +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_tx +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxen_d +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcoll +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcrs +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcrs_lost +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_collision_in_half_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/collision_in_full_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_tx_half_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_rx_half_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/carrier_sense_in_tx_full_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_rx_full_duplex +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/real_carrier_sense +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_mem_addr_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_mem_data_in +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_cnt +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_preamble_ok +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_sfd_ok +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_byte_aligned_ok +add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_len +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {476613 ns} +WaveRestoreZoom {476105 ns} {478586 ns} +configure wave -namecolwidth 280 +configure wave -valuecolwidth 68 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 Index: modelsim_sim/bin/work/_info =================================================================== --- modelsim_sim/bin/work/_info (nonexistent) +++ modelsim_sim/bin/work/_info (revision 338) @@ -0,0 +1,4 @@ +m255 +o +cModel Technology +dC:\Modeltech_5.6a\examples Index: modelsim_sim/bin/work/dir.keeper =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: modelsim_sim/bin/work/dir.keeper =================================================================== --- modelsim_sim/bin/work/dir.keeper (nonexistent) +++ modelsim_sim/bin/work/dir.keeper (revision 338)
modelsim_sim/bin/work/dir.keeper Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: modelsim_sim/bin/ethernet.mpf =================================================================== --- modelsim_sim/bin/ethernet.mpf (nonexistent) +++ modelsim_sim/bin/ethernet.mpf (revision 338) @@ -0,0 +1,406 @@ +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib + +work = work +[vcom] +; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). +; VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explict enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +VHDL93 = 0 +NoDebug = 0 +CheckSynthesis = 0 +NoVitalCheck = 0 +Optimize_1164 = 1 +NoVital = 0 +Quiet = 0 +Show_source = 0 +Show_Warning1 = 1 +Show_Warning2 = 1 +Show_Warning3 = 1 +Show_Warning4 = 1 +Show_Warning5 = 1 +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +Quiet = 0 +Show_source = 0 +NoDebug = 0 +Hazard = 0 +UpCase = 0 +OptionFile = ../../../../sim/rtl_sim/modelsim_sim/bin/vlog.opt +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +resolution = 1ns + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = ns + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired, or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less than the +; current ulimit setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Do not quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1; compress WLF file. +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in WLF file +; or only regions containing logged signals (0). +; The default is 0; log only regions with logged signals. +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0; no limit. Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0; no limit. +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0; do not delete WLF file when simulation ends. +; WLFDeleteOnQuit = 1 + +[lmc] +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so + +; ModelSim's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so +[Project] +Project_Version = 3 +Project_DefaultLib = work +Project_SortMethod = alpha +Project_Files_Count = 34 +Project_File_0 = ../../../../rtl/verilog/eth_registers.v +Project_File_P_0 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031654124 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 12 dont_compile 0 +Project_File_1 = ../../../../rtl/verilog/eth_crc.v +Project_File_P_1 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0 +Project_File_2 = ../../../../rtl/verilog/eth_random.v +Project_File_P_2 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0 +Project_File_3 = ../../../../bench/verilog/wb_bus_mon.v +Project_File_P_3 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 30 dont_compile 0 +Project_File_4 = ../../../../bench/verilog/tb_ethernet.v +Project_File_P_4 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1032198830 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 29 dont_compile 0 +Project_File_5 = ../../../../rtl/verilog/eth_outputcontrol.v +Project_File_P_5 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1026245520 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0 +Project_File_6 = ../../../../rtl/verilog/eth_transmitcontrol.v +Project_File_P_6 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 20 dont_compile 0 +Project_File_7 = ../../../../rtl/verilog/eth_top.v +Project_File_P_7 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842218 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 19 dont_compile 0 +Project_File_8 = ../../../../rtl/verilog/eth_rxaddrcheck.v +Project_File_P_8 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164866 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 13 dont_compile 0 +Project_File_9 = ../../../../bench/verilog/wb_model_defines.v +Project_File_P_9 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 33 dont_compile 0 +Project_File_10 = ../../../../rtl/verilog/eth_receivecontrol.v +Project_File_P_10 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0 +Project_File_11 = ../../../../rtl/verilog/eth_rxethmac.v +Project_File_P_11 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013843728 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 15 dont_compile 0 +Project_File_12 = ../../../../bench/verilog/eth_phy_defines.v +Project_File_P_12 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 27 dont_compile 0 +Project_File_13 = ../../../../rtl/verilog/eth_miim.v +Project_File_P_13 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349930 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0 +Project_File_14 = ../../../../rtl/verilog/eth_rxcounters.v +Project_File_P_14 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013771610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 14 dont_compile 0 +Project_File_15 = ../../../../rtl/verilog/eth_register.v +Project_File_P_15 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029535812 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0 +Project_File_16 = ../../../../bench/verilog/wb_slave_behavioral.v +Project_File_P_16 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 34 dont_compile 0 +Project_File_17 = ../../../../bench/verilog/wb_master_behavioral.v +Project_File_P_17 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 31 dont_compile 0 +Project_File_18 = ../../../../rtl/verilog/eth_txethmac.v +Project_File_P_18 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1014740642 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 22 dont_compile 0 +Project_File_19 = ../../../../rtl/verilog/eth_wishbone.v +Project_File_P_19 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031753926 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 24 dont_compile 0 +Project_File_20 = ../../../../rtl/verilog/eth_txcounters.v +Project_File_P_20 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019487254 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 21 dont_compile 0 +Project_File_21 = ../../../../bench/verilog/eth_phy.v +Project_File_P_21 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031928616 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 26 dont_compile 0 +Project_File_22 = ../../../../bench/verilog/wb_master32.v +Project_File_P_22 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 32 dont_compile 0 +Project_File_23 = ../../../../rtl/verilog/eth_rxstatem.v +Project_File_P_23 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 16 dont_compile 0 +Project_File_24 = ../../../../bench/verilog/tb_eth_defines.v +Project_File_P_24 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031942506 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 28 dont_compile 0 +Project_File_25 = ../../../../rtl/verilog/eth_maccontrol.v +Project_File_P_25 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0 +Project_File_26 = ../../../../rtl/verilog/eth_txstatem.v +Project_File_P_26 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 23 dont_compile 0 +Project_File_27 = ../../../../rtl/verilog/eth_shiftreg.v +Project_File_P_27 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349020 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 17 dont_compile 0 +Project_File_28 = ../../../../rtl/verilog/eth_spram_256x32.v +Project_File_P_28 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1027442170 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 18 dont_compile 0 +Project_File_29 = ../../../../rtl/verilog/eth_fifo.v +Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0 +Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v +Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0 +Project_File_31 = ../../../../rtl/verilog/eth_defines.v +Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0 +Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v +Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0 +Project_File_33 = ../../../../rtl/verilog/timescale.v +Project_File_P_33 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 25 dont_compile 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 Index: modelsim_sim/bin/do.do =================================================================== --- modelsim_sim/bin/do.do (nonexistent) +++ modelsim_sim/bin/do.do (revision 338) @@ -0,0 +1,48 @@ +#///////////////////////////////////////////////////////////////////// +#/// //// +#/// do.do //// +#/// //// +#/// This file is part of the Ethernet IP core project //// +#/// http://www.opencores.org/projects/ethmac/ //// +#/// //// +#/// Author(s): //// +#/// - Igor Mohor (igorM@opencores.org) //// +#/// //// +#/// All additional information is avaliable in the Readme.txt //// +#/// file. //// +#/// //// +#///////////////////////////////////////////////////////////////////// +#/// //// +#/// Copyright (C) 2001, 2002 Authors //// +#/// //// +#/// This source file may be used and distributed without //// +#/// restriction provided that this copyright statement is not //// +#/// removed from the file and that any derivative work contains //// +#/// the original copyright notice and the associated disclaimer. //// +#/// //// +#/// This source file is free software; you can redistribute it //// +#/// and/or modify it under the terms of the GNU Lesser General //// +#/// Public License as published by the Free Software Foundation; //// +#/// either version 2.1 of the License, or (at your option) any //// +#/// later version. //// +#/// //// +#/// This source is distributed in the hope that it will be //// +#/// useful, but WITHOUT ANY WARRANTY; without even the implied //// +#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +#/// PURPOSE. See the GNU Lesser General Public License for more //// +#/// details. //// +#/// //// +#/// You should have received a copy of the GNU Lesser General //// +#/// Public License along with this source; if not, download it //// +#/// from http://www.opencores.org/lgpl.shtml //// +#/// //// +#///////////////////////////////////////////////////////////////////// +#/ +#/ CVS Revision History +#/ +#/ $Log: not supported by cvs2svn $ +#/ +#/ +#/ + +do ../run/tb_eth.do Index: modelsim_sim/bin/vlog.opt =================================================================== --- modelsim_sim/bin/vlog.opt (nonexistent) +++ modelsim_sim/bin/vlog.opt (revision 338) @@ -0,0 +1,2 @@ ++incdir+../../../../bench/verilog ++incdir+../../../../rtl/verilog Index: modelsim_sim/log/dir.keeper =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: modelsim_sim/log/dir.keeper =================================================================== --- modelsim_sim/log/dir.keeper (nonexistent) +++ modelsim_sim/log/dir.keeper (revision 338)
modelsim_sim/log/dir.keeper Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: modelsim_sim/out/dir.keeper =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: modelsim_sim/out/dir.keeper =================================================================== --- modelsim_sim/out/dir.keeper (nonexistent) +++ modelsim_sim/out/dir.keeper (revision 338)
modelsim_sim/out/dir.keeper Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ncsim_sim/bin/sim_file_list.lst =================================================================== --- ncsim_sim/bin/sim_file_list.lst (nonexistent) +++ ncsim_sim/bin/sim_file_list.lst (revision 338) @@ -0,0 +1,10 @@ +../../../../bench/verilog/tb_ethernet.v +../../../../bench/verilog/tb_eth_defines.v +../../../../bench/verilog/eth_phy.v +../../../../bench/verilog/eth_phy_defines.v +../../../../bench/verilog/wb_bus_mon.v +../../../../bench/verilog/wb_slave_behavioral.v +../../../../bench/verilog/wb_master32.v +../../../../bench/verilog/wb_master_behavioral.v +../../../../../../lib/vs_rams/018/vs_hdsp_256x32/vs_hdsp_256x32.v + Index: ncsim_sim/bin/xilinx_file_list.lst =================================================================== --- ncsim_sim/bin/xilinx_file_list.lst (nonexistent) +++ ncsim_sim/bin/xilinx_file_list.lst (revision 338) @@ -0,0 +1,4 @@ +../../../../../../lib/xilinx/lib/glbl/glbl.v +../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v +../../../../../../lib/xilinx/lib/unisims/RAMB4_S16.v +../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v Index: ncsim_sim/bin/artisan_file_list.lst =================================================================== --- ncsim_sim/bin/artisan_file_list.lst (nonexistent) +++ ncsim_sim/bin/artisan_file_list.lst (revision 338) @@ -0,0 +1,8 @@ +-cdslib ../bin/cds.lib +-hdlvar ../bin/hdl.var +-logfile ../log/ncvlog_artisan.log +-update +-messages +../../../../../../lib/artisan/art_hsdp_256x40.v +../../../../../../lib/artisan/art_hddp_8192x64.v + Index: ncsim_sim/bin/rtl_file_list.lst =================================================================== --- ncsim_sim/bin/rtl_file_list.lst (nonexistent) +++ ncsim_sim/bin/rtl_file_list.lst (revision 338) @@ -0,0 +1,25 @@ +../../../../rtl/verilog/eth_crc.v +../../../../rtl/verilog/eth_defines.v +../../../../rtl/verilog/eth_maccontrol.v +../../../../rtl/verilog/eth_macstatus.v +../../../../rtl/verilog/eth_miim.v +../../../../rtl/verilog/eth_outputcontrol.v +../../../../rtl/verilog/eth_random.v +../../../../rtl/verilog/eth_receivecontrol.v +../../../../rtl/verilog/eth_register.v +../../../../rtl/verilog/eth_registers.v +../../../../rtl/verilog/eth_rxcounters.v +../../../../rtl/verilog/eth_rxethmac.v +../../../../rtl/verilog/eth_rxstatem.v +../../../../rtl/verilog/eth_shiftreg.v +../../../../rtl/verilog/timescale.v +../../../../rtl/verilog/eth_top.v +../../../../rtl/verilog/eth_transmitcontrol.v +../../../../rtl/verilog/eth_txcounters.v +../../../../rtl/verilog/eth_txethmac.v +../../../../rtl/verilog/eth_txstatem.v +../../../../rtl/verilog/eth_clockgen.v +../../../../rtl/verilog/eth_spram_256x32.v +../../../../rtl/verilog/eth_wishbone.v +../../../../rtl/verilog/eth_fifo.v +../../../../rtl/verilog/eth_rxaddrcheck.v Index: ncsim_sim/bin/INCA_libs/worklib/dir_keeper =================================================================== Index: ncsim_sim/bin/ncelab.args =================================================================== --- ncsim_sim/bin/ncelab.args (nonexistent) +++ ncsim_sim/bin/ncelab.args (revision 338) @@ -0,0 +1,7 @@ +-snapshot worklib.ethernet:fun +-cdslib ../bin/cds.lib +-logfile ../log/ncelab.log +-access +wc +-messages +-no_tchk_msg +-v93 worklib.tb_ethernet Index: ncsim_sim/bin/ncsim_waves.rc =================================================================== --- ncsim_sim/bin/ncsim_waves.rc (nonexistent) +++ ncsim_sim/bin/ncsim_waves.rc (revision 338) @@ -0,0 +1,7 @@ +set dump_level all + +database -open waves -shm -into ../out/waves.shm +probe -create -database waves tb_ethernet -shm -all -depth $dump_level + +run +quit Index: ncsim_sim/bin/ncelab_xilinx.args =================================================================== --- ncsim_sim/bin/ncelab_xilinx.args (nonexistent) +++ ncsim_sim/bin/ncelab_xilinx.args (revision 338) @@ -0,0 +1,9 @@ +-snapshot worklib.ethernet:fun +-cdslib ../bin/cds.lib +-hdlvar ../bin/hdl.var +-logfile ../log/ncelab_xilinx.log +-access +wc +-messages +-no_tchk_msg +-v93 +worklib.tb_ethernet worklib.glbl Index: ncsim_sim/bin/ncsim.rc =================================================================== --- ncsim_sim/bin/ncsim.rc (nonexistent) +++ ncsim_sim/bin/ncsim.rc (revision 338) @@ -0,0 +1,2 @@ +run +quit Index: ncsim_sim/bin/cds.lib =================================================================== --- ncsim_sim/bin/cds.lib (nonexistent) +++ ncsim_sim/bin/cds.lib (revision 338) @@ -0,0 +1,2 @@ +define worklib ../bin/INCA_libs/worklib +include $CDS_INST_DIR/tools/inca/files/cds.lib Index: ncsim_sim/bin/hdl.var =================================================================== --- ncsim_sim/bin/hdl.var (nonexistent) +++ ncsim_sim/bin/hdl.var (revision 338) @@ -0,0 +1,9 @@ +# +# hdl.var: Defines variables used by the INCA tools. +# Created by ncprep on Sat Aug 4 10:51:23 2001 +# + +softinclude $CDS_INST_DIR/tools/inca/files/hdl.var + +define LIB_MAP ( $LIB_MAP, + => worklib ) +define VIEW_MAP ( $VIEW_MAP, .v => v) Index: ncsim_sim/run/run_eth_sim_regr.scr =================================================================== --- ncsim_sim/run/run_eth_sim_regr.scr (nonexistent) +++ ncsim_sim/run/run_eth_sim_regr.scr (revision 338) @@ -0,0 +1,200 @@ +#!/bin/csh -f + +set arg_num = $#; # number of arguments + +# current iterration +set iter = 1; +# number of tests with DEFINES + test with user defined constants! +set all_iterations = 3; + +# Process argument +set arg_waves = 0; +set arg_regression = 0; + +if ($arg_num == 0) then + echo " Verification without any parameter !" +else + if ($arg_num == 1) then + if ($1 == "waves") then + @ arg_waves = 1; + echo " Verification with parameter : waves !" + else + if ($1 == "regression") then + @ arg_regression = 1; + echo " Verification with parameter : regression !" + else + echo " Not correct parameter ( $1 )" + echo " Correct parameters are:" + echo " - waves" + echo " - regression" + exit + endif + endif + else + if ($arg_num == 2) then + if ($1 == "waves") then + @ arg_waves = 1; + if ($2 == "regression") then + @ arg_regression = 1; + echo " Verification with parameter : waves, regression !" + else + echo " Not correct parameter ( $2 )" + echo " Correct 2. parameter is:" + echo " - regression" + exit + endif + else + if ($1 == "regression") then + @ arg_regression = 1; + if ($2 == "waves") then + @ arg_waves = 1; + echo " Verification with parameter : waves, regression !" + else + echo " Not correct parameter ( $2 )" + echo " Correct 2. parameter is:" + echo " - waves" + exit + endif + else + echo " Not correct parameter ( $1 )" + echo " Correct parameters are:" + echo " - waves" + echo " - regression" + exit + endif + endif + else + echo " Too many parameters ( $arg_num )" + echo " Maximum number of parameters is 2:" + echo " - waves" + echo " - regression" + exit + endif + endif +endif + +echo "" +echo "<<<" +echo "<<< Ethernet MAC VERIFICATION " +echo "<<<" + +# ITERATION LOOP +iteration: + +echo "" +echo "<<<" +echo "<<< Iteration ${iter}" +echo "<<<" + +if ($arg_regression == 1) then + if ($iter <= $all_iterations) then + if ($iter == 1) then + echo "<<< Defines:" + echo "\tEthernet with GENERIC RAM" + echo "-DEFINE REGR" > ./defines.args + endif + if ($iter == 2) then + echo "<<< Defines:" + echo "\tEthernet with XILINX DISTRIBUTED RAM" + echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ./defines.args + endif + if ($iter == 3) then + echo "<<< Defines:" + echo "\tEthernet with XILINX BLOCK RAM" + echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ./defines.args + endif + endif +endif + +# Run NC-Verilog compiler +echo "" +echo "\t@@@" +echo "\t@@@ Compiling sources" +echo "\t@@@" + +# creating .args file for ncvlog and adding main parameters +echo "-cdslib ../bin/cds.lib" > ./ncvlog.args +echo "-hdlvar ../bin/hdl.var" >> ./ncvlog.args +echo "-logfile ../log/ncvlog.log" >> ./ncvlog.args +echo "-update" >> ./ncvlog.args +echo "-messages" >> ./ncvlog.args +echo "-INCDIR ../../../../bench/verilog" >> ./ncvlog.args +echo "-INCDIR ../../../../rtl/verilog" >> ./ncvlog.args +echo "-DEFINE SIM" >> ./ncvlog.args +# adding defines to .args file +if ($arg_regression == 1) then + cat ./defines.args >> ./ncvlog.args +endif +# adding RTL and Sim files to .args file +cat ../bin/rtl_file_list.lst >> ./ncvlog.args +cat ../bin/sim_file_list.lst >> ./ncvlog.args +# adding device dependent files to .args file +cat ../bin/xilinx_file_list.lst >> ./ncvlog.args + +ncvlog -file ./ncvlog.args# > /dev/null; +echo "" + + +# Run the NC-Verilog elaborator (build the design hierarchy) +echo "" +echo "\t@@@" +echo "\t@@@ Building design hierarchy (elaboration)" +echo "\t@@@" +ncelab -file ../bin/ncelab_xilinx.args# > /dev/null; +echo "" + + +# Run the NC-Verilog simulator (simulate the design) +echo "" +echo "\t###" +echo "\t### Running tests (this takes a long time!)" +echo "\t###" + +# creating ncsim.args file for ncsim and adding main parameters +echo "-cdslib ../bin/cds.lib" > ./ncsim.args +echo "-hdlvar ../bin/hdl.var" >> ./ncsim.args +echo "-logfile ../log/ncsim.log" >> ./ncsim.args +echo "-messages" >> ./ncsim.args +if ($arg_waves == 1) then + echo "-input ../bin/ncsim_waves.rc" >> ./ncsim.args +else + echo "-input ../bin/ncsim.rc" >> ./ncsim.args +endif +echo "worklib.ethernet:fun" >> ./ncsim.args + +ncsim -file ./ncsim.args# > /dev/null +if ($status != 0) then + echo "" + echo "TESTS couldn't start due to Errors!" + echo "" + exit +else + if ($arg_regression == 1) then + if ($arg_waves == 1) then + mv ../out/waves.shm ../out/i${iter}_waves.shm + endif + mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log + mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log + mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log + mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log + mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log + mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log + endif +endif +echo "" + +@ iter += 1; + +if (($arg_regression == 1) && ($iter <= $all_iterations)) then + goto iteration +else +# rm ./defines.args + echo "" + echo "<<<" + echo "<<< End of VERIFICATION" + echo "<<<" + echo "<<<" + echo "<<< -------------------------------------------------" + echo "<<<" +endif + Index: ncsim_sim/run/clean =================================================================== --- ncsim_sim/run/clean (nonexistent) +++ ncsim_sim/run/clean (revision 338) @@ -0,0 +1,4 @@ +rm ../bin/INCA_libs/worklib/* +rm ../bin/INCA_libs/worklib/.* +rm ../log/*.log +rm -rf ../out/*.shm Index: ncsim_sim/run/top_groups.do =================================================================== --- ncsim_sim/run/top_groups.do (nonexistent) +++ ncsim_sim/run/top_groups.do (revision 338) @@ -0,0 +1,292 @@ +// Signalscan Version 6.7p1 + + +define noactivityindicator +define analog waveform lines +define add variable default overlay off +define waveform window analogheight 1 +define terminal automatic +define buttons control \ + 1 opensimmulationfile \ + 2 executedofile \ + 3 designbrowser \ + 4 waveform \ + 5 source \ + 6 breakpoints \ + 7 definesourcessearchpath \ + 8 exit \ + 9 createbreakpoint \ + 10 creategroup \ + 11 createmarker \ + 12 closesimmulationfile \ + 13 renamesimmulationfile \ + 14 replacesimulationfiledata \ + 15 listopensimmulationfiles \ + 16 savedofile +define buttons waveform \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 zoomin \ + 7 zoomout \ + 8 zoomoutfull \ + 9 expand \ + 10 createmarker \ + 11 designbrowser:1 \ + 12 variableradixbinary \ + 13 variableradixoctal \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons designbrowser \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 cdupscope \ + 7 getallvariables \ + 8 getdeepallvariables \ + 9 addvariables \ + 10 addvarsandclosewindow \ + 11 closewindow \ + 12 scopefiltermodule \ + 13 scopefiltertask \ + 14 scopefilterfunction \ + 15 scopefilterblock \ + 16 scopefilterprimitive +define buttons event \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 move \ + 7 closewindow \ + 8 duplicate \ + 9 defineasrisingedge \ + 10 defineasfallingedge \ + 11 defineasanyedge \ + 12 variableradixbinary \ + 13 variableradixoctal \ + 14 variableradixdecimal \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define buttons source \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createbreakpoint \ + 7 creategroup \ + 8 createmarker \ + 9 createevent \ + 10 createregisterpage \ + 11 closewindow \ + 12 opensimmulationfile \ + 13 closesimmulationfile \ + 14 renamesimmulationfile \ + 15 replacesimulationfiledata \ + 16 listopensimmulationfiles +define buttons register \ + 1 undo \ + 2 cut \ + 3 copy \ + 4 paste \ + 5 delete \ + 6 createregisterpage \ + 7 closewindow \ + 8 continuefor \ + 9 continueuntil \ + 10 continueforever \ + 11 stop \ + 12 previous \ + 13 next \ + 14 variableradixbinary \ + 15 variableradixhexadecimal \ + 16 variableradixascii +define show related transactions +define exit prompt +define event search direction forward +define variable nofullhierarchy +define variable nofilenames +define variable nofullpathfilenames +include bookmark with filenames +include scope history without filenames +define waveform window listpane 4.96 +define waveform window namepane 15.18 +define multivalueindication +define pattern curpos dot +define pattern cursor1 dot +define pattern cursor2 dot +define pattern marker dot +define print designer "Miha Dolenc" +define print border +define print color blackonwhite +define print command "/usr/ucb/lpr -P%P" +define print printer lp +define print range visible +define print variable visible +define rise fall time low threshold percentage 10 +define rise fall time high threshold percentage 90 +define rise fall time low value 0 +define rise fall time high value 3.3 +define sendmail command "/usr/lib/sendmail" +define sequence time width 30.00 +define snap + +define source noprompt +define time units default +define userdefinedbussymbol +define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html" +define waveform window grid off +define waveform window waveheight 14 +define waveform window wavespace 6 +define web browser command netscape +define zoom outfull on initial add off +add group \ + A \ + +add group \ + "WISHBONE common" \ + tb_ethernet.eth_top.wb_clk_i \ + tb_ethernet.eth_top.wb_rst_i \ + tb_ethernet.eth_top.wb_dat_i[31:0]'h \ + tb_ethernet.eth_top.wb_dat_o[31:0]'h \ + tb_ethernet.eth_top.wb_err_o \ + +add group \ + "WISHBONE slave signals" \ + tb_ethernet.eth_top.wb_adr_i[11:2]'h \ + tb_ethernet.eth_top.wb_sel_i[3:0]'h \ + tb_ethernet.eth_top.wb_we_i \ + tb_ethernet.eth_top.wb_cyc_i \ + tb_ethernet.eth_top.wb_stb_i \ + tb_ethernet.eth_top.wb_ack_o \ + +add group \ + "WISHBONE master signals" \ + tb_ethernet.eth_top.m_wb_adr_o[31:0]'h \ + tb_ethernet.eth_top.m_wb_sel_o[3:0]'h \ + tb_ethernet.eth_top.m_wb_we_o \ + tb_ethernet.eth_top.m_wb_dat_i[31:0]'h \ + tb_ethernet.eth_top.m_wb_dat_o[31:0]'h \ + tb_ethernet.eth_top.m_wb_cyc_o \ + tb_ethernet.eth_top.m_wb_stb_o \ + tb_ethernet.eth_top.m_wb_ack_i \ + tb_ethernet.eth_top.m_wb_err_i \ + +add group \ + "MAC common" \ + tb_ethernet.eth_top.mcoll_pad_i \ + tb_ethernet.eth_top.mcrs_pad_i \ + +add group \ + "MAC TX" \ + tb_ethernet.eth_top.mtx_clk_pad_i \ + tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \ + tb_ethernet.eth_top.mtxen_pad_o \ + tb_ethernet.eth_top.mtxerr_pad_o \ + +add group \ + "MAC RX" \ + tb_ethernet.eth_top.mrx_clk_pad_i \ + tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \ + tb_ethernet.eth_top.mrxdv_pad_i \ + tb_ethernet.eth_top.mrxerr_pad_i \ + +add group \ + "MAC MIIM interface" \ + tb_ethernet.eth_top.mdc_pad_o \ + tb_ethernet.eth_top.md_padoe_o \ + tb_ethernet.eth_top.md_pad_o \ + tb_ethernet.eth_top.md_pad_i \ + tb_ethernet.eth_top.miim1.Busy \ + tb_ethernet.eth_top.miim1.LinkFail \ + tb_ethernet.eth_top.miim1.Nvalid \ + tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \ + tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \ + tb_ethernet.eth_top.miim1.Prsd[15:0]'h \ + tb_ethernet.eth_top.miim1.Divider[7:0]'h \ + +add group \ + "Test signals" \ + tb_ethernet.test_name[799:0]'a \ + tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \ + tb_ethernet.eth_top.miim1.InProgress \ + tb_ethernet.eth_top.miim1.InProgress_q1 \ + tb_ethernet.eth_top.miim1.InProgress_q2 \ + tb_ethernet.eth_top.miim1.InProgress_q3 \ + tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \ + tb_ethernet.eth_phy.status_bit6_0[6:0]'h \ + tb_ethernet.eth_phy.control_bit8_0[8:0]'h \ + tb_ethernet.eth_phy.control_bit9 \ + tb_ethernet.eth_phy.control_bit14_10[14:10]'h \ + tb_ethernet.eth_phy.control_bit15 \ + tb_ethernet.eth_phy.eth_speed \ + tb_ethernet.eth_phy.m_rst_n_i \ + tb_ethernet.eth_phy.mcoll_o \ + tb_ethernet.eth_phy.mcrs_o \ + tb_ethernet.eth_phy.md_get_phy_address \ + tb_ethernet.eth_phy.md_get_reg_address \ + tb_ethernet.eth_phy.md_get_reg_data_in \ + tb_ethernet.eth_phy.md_put_reg_data_in \ + tb_ethernet.eth_phy.md_put_reg_data_out \ + tb_ethernet.eth_phy.reg_data_in[15:0]'h \ + tb_ethernet.eth_phy.reg_data_out[15:0]'h \ + tb_ethernet.eth_phy.register_bus_in[15:0]'h \ + tb_ethernet.eth_phy.register_bus_out[15:0]'h \ + tb_ethernet.eth_phy.reg_address[4:0]'h \ + tb_ethernet.eth_phy.md_io_output \ + tb_ethernet.eth_phy.md_io_enable \ + tb_ethernet.eth_phy.md_io \ + tb_ethernet.Mdc_O \ + tb_ethernet.Mdi_I \ + tb_ethernet.Mdio_IO \ + tb_ethernet.Mdo_O \ + tb_ethernet.Mdo_OE \ + tb_ethernet.eth_phy.md_io_enable \ + tb_ethernet.eth_phy.md_io_output \ + tb_ethernet.eth_phy.md_io_rd_wr \ + tb_ethernet.eth_phy.md_io_reg \ + tb_ethernet.eth_phy.m_rst_n_i \ + tb_ethernet.eth_phy.md_transfer_cnt'd \ + tb_ethernet.eth_phy.md_transfer_cnt_reset \ + tb_ethernet.eth_phy.mdc_i \ + tb_ethernet.eth_phy.mrx_clk_o \ + tb_ethernet.eth_phy.mrxd_o[3:0]'h \ + tb_ethernet.eth_phy.mrxdv_o \ + tb_ethernet.eth_phy.mrxerr_o \ + tb_ethernet.eth_phy.mtx_clk_o \ + tb_ethernet.eth_phy.mtxd_i[3:0]'h \ + tb_ethernet.eth_phy.mtxen_i \ + tb_ethernet.eth_phy.mtxerr_i \ + tb_ethernet.eth_phy.phy_address[4:0]'h \ + tb_ethernet.eth_phy.phy_id1[15:0]'h \ + tb_ethernet.eth_phy.phy_id2[15:0]'h \ + tb_ethernet.eth_phy.phy_log[31:0]'h \ + tb_ethernet.eth_phy.reg_address[4:0]'h \ + tb_ethernet.eth_phy.register_bus_in[15:0]'h \ + tb_ethernet.eth_phy.register_bus_out[15:0]'h \ + tb_ethernet.eth_phy.registers_addr_data_test_operation \ + tb_ethernet.eth_phy.rx_link_down_halfperiod \ + ( \ + minmax 0 93 \ + ) \ + tb_ethernet.eth_phy.self_clear_d0 \ + tb_ethernet.eth_phy.self_clear_d1 \ + tb_ethernet.eth_phy.self_clear_d2 \ + tb_ethernet.eth_phy.self_clear_d3 \ + tb_ethernet.eth_phy.status_bit6_0[6:0]'h \ + tb_ethernet.eth_phy.status_bit7 \ + tb_ethernet.eth_phy.status_bit8 \ + tb_ethernet.eth_phy.status_bit15_9[15:9]'h \ + + +deselect all +open window designbrowser 1 geometry 56 117 855 550 +open window waveform 1 geometry 10 59 1592 1094 +zoom at 4981823.979(0)ns 0.00025639 0.00000000 Index: ncsim_sim/log/dir_keeper =================================================================== Index: ncsim_sim/out/dir_keeper ===================================================================

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