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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /ethmac/trunk/rtl/verilog
    from Rev 338 to Rev 341
    Reverse comparison

Rev 338 → Rev 341

/eth_rxethmac.v
3,12 → 3,13
//// eth_rxethmac.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// http://www.opencores.org/projects,ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
//// - Olof Kindgren (olof@opencores.org ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
15,7 → 16,7
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// Copyright (C) 2011 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
40,8 → 41,12
//// ////
//////////////////////////////////////////////////////////////////////
//
// 2011-07-06 Olof Kindgren <olof@opencores.org>
// Add ByteCntEq0 to rxaddrcheck
//
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
221,7 → 226,7
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.HASH0(r_HASH0), .HASH1(r_HASH1), .ByteCntEq0(ByteCntEq0),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
/eth_rxaddrcheck.v
3,10 → 3,11
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// http://www.opencores.org/project,ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer (billditt@aol.com) ////
//// - Olof Kindgren (olof@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
13,7 → 14,7
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// Copyright (C) 2011 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
38,10 → 39,16
//// ////
//////////////////////////////////////////////////////////////////////
//
// 2011-07-06 Olof Kindgren <olof@opencores.org>
// Reset AdressMiss when a new frame arrives. Otherwise it will report
// the last value when a frame is less than seven bytes
//
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/11/19 17:34:52 mohor
//
// // Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
69,7 → 76,7
 
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
83,6 → 90,7
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq0;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
143,6 → 151,8
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq0)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end

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