URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac/trunk/sim/rtl_sim
- from Rev 338 to Rev 356
- ↔ Reverse comparison
Rev 338 → Rev 356
/modelsim_sim/run/tb_eth.do
63,7 → 63,7
|
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_clockgen.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_crc.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_defines.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/ethmac_defines.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_fifo.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_maccontrol.v} |
vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_macstatus.v} |
/modelsim_sim/bin/ethernet.mpf
396,7 → 396,7
Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0 |
Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v |
Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0 |
Project_File_31 = ../../../../rtl/verilog/eth_defines.v |
Project_File_31 = ../../../../rtl/verilog/ethmac_defines.v |
Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0 |
Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v |
Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0 |
/ncsim_sim/bin/rtl_file_list.lst
1,5 → 1,5
../../../../rtl/verilog/eth_crc.v |
../../../../rtl/verilog/eth_defines.v |
../../../../rtl/verilog/ethmac_defines.v |
../../../../rtl/verilog/eth_maccontrol.v |
../../../../rtl/verilog/eth_macstatus.v |
../../../../rtl/verilog/eth_miim.v |
/bin/rtl_file_list.lst
1,5 → 1,5
../../../rtl/verilog/eth_crc.v |
../../../rtl/verilog/eth_defines.v |
../../../rtl/verilog/ethmac_defines.v |
../../../rtl/verilog/eth_maccontrol.v |
../../../rtl/verilog/eth_macstatus.v |
../../../rtl/verilog/eth_miim.v |