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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /ethmac/trunk
    from Rev 352 to Rev 353
    Reverse comparison

Rev 352 → Rev 353

/rtl/verilog/eth_rxcounters.v
144,30 → 144,30
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
 
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
 
186,7 → 186,7
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
 
208,7 → 208,7
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
 
/rtl/verilog/eth_txethmac.v
1,7 → 1,7
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
339,7 → 339,7
RetryCnt[3:0] <= 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
RetryCnt[3:0] <= RetryCnt[3:0] + 1;
end
end
 
/rtl/verilog/eth_txcounters.v
157,7 → 157,7
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 1'b1;
NibCnt <= NibCnt + 16'd1;
end
end
 
165,11 → 165,11
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
 
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
 
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
 
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
 
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
189,7 → 189,7
ByteCnt[15:0] <= 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
210,7 → 210,7
DlyCrcCnt <= 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
end
 
/rtl/verilog/eth_receivecontrol.v
299,7 → 299,7
DlyCrcCnt <= 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
 
317,7 → 317,7
ByteCnt[4:0] <= 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;
end
 
 
350,7 → 350,7
PauseTimer[15:0] <= LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
411,7 → 411,7
SlotTimer[5:0] <= 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;
end
 
 
/rtl/verilog/eth_clockgen.v
87,7 → 87,7
 
 
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
 
 
// Counter counts half period
/rtl/verilog/eth_transmitcontrol.v
250,7 → 250,7
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
 
269,10 → 269,10
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
 
 

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