URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac
- from Rev 348 to Rev 349
- ↔ Reverse comparison
Rev 348 → Rev 349
/trunk/rtl/verilog/eth_rxethmac.v
198,7 → 198,8
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// Rx State Machine module |
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0), |
eth_rxstatem #(.Tp(Tp)) |
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0), |
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5), |
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame), |
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble), |
207,7 → 208,8
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// Rx Counters module |
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle), |
eth_rxcounters #(.Tp(Tp)) |
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle), |
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop), |
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn), |
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG), |
221,7 → 223,8
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// Rx Address Check |
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eth_rxaddrcheck rxaddrcheck1 |
eth_rxaddrcheck #(.Tp(Tp)) |
rxaddrcheck1 |
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), |
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), |
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2), |
244,7 → 247,8
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// Connecting module Crc |
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
eth_crc #(.Tp(Tp)) |
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
.Crc(Crc), .CrcError(CrcError) |
); |
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/trunk/rtl/verilog/eth_txethmac.v
435,7 → 435,8
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// Connecting module Counters |
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), |
eth_txcounters #(.Tp(Tp)) |
txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), |
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff), |
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG), |
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk), |
448,7 → 449,8
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// Connecting module StateM |
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), |
eth_txstatem #(.Tp(Tp)) |
txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), |
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD), |
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision), |
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7), |
477,13 → 479,15
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// Connecting module Crc |
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
eth_crc #(.Tp(Tp)) |
txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
.Crc(Crc), .CrcError(CrcError) |
); |
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// Connecting module Random |
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), |
eth_random #(.Tp(Tp)) |
random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), |
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt)); |
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/trunk/rtl/verilog/eth_wishbone.v
309,6 → 309,12
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parameter Tp = 1; |
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
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// WISHBONE common |
1006,8 → 1012,8
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
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1158,7 → 1164,7
cyc_cleared<=#Tp 1'b1; |
IncrTxPointer<=#Tp 1'b0; |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
rx_burst_cnt<=#Tp 0; |
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
1182,7 → 1188,7
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access) |
begin |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
end |
default: // Don't touch |
begin |
1201,7 → 1207,10
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assign TxFifoClear = (TxAbortPacket | TxRetryPacket); |
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eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH) |
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.DEPTH(TX_FIFO_DEPTH), |
.CNT_WIDTH(TX_FIFO_CNT_WIDTH), |
.Tp(Tp)) |
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb), |
.clk(WB_CLK_I), .reset(Reset), |
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), |
2196,8 → 2205,10
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assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; |
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eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH) |
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.DEPTH(RX_FIFO_DEPTH), |
.CNT_WIDTH(RX_FIFO_CNT_WIDTH), |
.Tp(Tp)) |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), |
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i), |
/trunk/rtl/verilog/eth_miim.v
430,17 → 430,20
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// Connecting the Clock Generator Module |
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
eth_clockgen #(.Tp(Tp)) |
clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
); |
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// Connecting the Shift Register Module |
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
eth_shiftreg #(.Tp(Tp)) |
shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), |
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) |
); |
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// Connecting the Output Control Module |
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
eth_outputcontrol #(.Tp(Tp)) |
outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), |
.Mdo(Mdo), .MdoEn(MdoEn) |
); |
/trunk/rtl/verilog/eth_maccontrol.v
245,7 → 245,8
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// Connecting receivecontrol module |
eth_receivecontrol receivecontrol1 |
eth_receivecontrol #(.Tp(Tp)) |
receivecontrol1 |
( |
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), |
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), |
257,7 → 258,8
); |
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eth_transmitcontrol transmitcontrol1 |
eth_transmitcontrol #(.Tp(Tp)) |
transmitcontrol1 |
( |
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut), |
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq), |
/trunk/rtl/verilog/eth_top.v
279,6 → 279,12
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parameter Tp = 1; |
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
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// WISHBONE common |
383,7 → 389,8
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// Connecting Miim module |
eth_miim miim1 |
eth_miim #(.Tp(Tp)) |
miim1 |
( |
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv), |
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD), |
542,7 → 549,8
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// Connecting Ethernet registers |
eth_registers ethreg1 |
eth_registers #(.Tp(Tp)) |
ethreg1 |
( |
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i), |
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i), |
599,7 → 607,8
wire [1:0] StateData; |
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// Connecting MACControl |
eth_maccontrol maccontrol1 |
eth_maccontrol #(.Tp(Tp)) |
maccontrol1 |
( |
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq), |
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData), |
652,7 → 661,8
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// Connecting TxEthMAC |
eth_txethmac txethmac1 |
eth_txethmac #(.Tp(Tp)) |
txethmac1 |
( |
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense), |
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut), |
686,7 → 696,8
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// Connecting RxEthMAC |
eth_rxethmac rxethmac1 |
eth_rxethmac #(.Tp(Tp)) |
rxethmac1 |
( |
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb), |
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), |
882,7 → 893,14
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// Connecting Wishbone module |
eth_wishbone wishbone |
eth_wishbone #(.Tp(Tp), |
.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.TX_FIFO_DEPTH (TX_FIFO_DEPTH), |
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH), |
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.RX_FIFO_DEPTH (RX_FIFO_DEPTH), |
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH)) |
wishbone |
( |
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i), |
.WB_DAT_O(BD_WB_DAT_O), |
941,7 → 959,8
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; |
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// Connecting MacStatus module |
eth_macstatus macstatus1 |
eth_macstatus #(.Tp(Tp)) |
macstatus1 |
( |
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), |