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Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path 
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    from Rev 105 to Rev 106
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Rev 105 → Rev 106

/trunk/rtl/verilog/eth_defines.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.16 2002/03/19 12:53:29 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
171,7 → 175,7
 
 
// Outputs are registered (uncomment when needed)
//`define ETH_REGISTERED_OUTPUTS
`define ETH_REGISTERED_OUTPUTS
 
`define TX_FIFO_CNT_WIDTH 5
`define TX_FIFO_DEPTH 16
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
362,16 → 366,11
wire SetGotData;
wire GotDataEvaluate;
 
reg temp_ack;
reg WB_ACK_O;
 
wire [6:0] RxStatusIn;
reg [6:0] RxStatusInLatched;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_ack2;
reg [31:0] registered_ram_do;
`endif
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
396,31 → 395,16
begin
if(Reset)
begin
temp_ack <=#Tp 1'b0;
`ifdef ETH_REGISTERED_OUTPUTS
temp_ack2 <=#Tp 1'b0;
registered_ram_do <=#Tp 32'h0;
`endif
WB_ACK_O <=#Tp 1'b0;
end
else
begin
temp_ack <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
`ifdef ETH_REGISTERED_OUTPUTS
temp_ack2 <=#Tp temp_ack;
registered_ram_do <=#Tp ram_do;
`endif
WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
end
 
`ifdef ETH_REGISTERED_OUTPUTS
assign WB_ACK_O = temp_ack2;
assign WB_DAT_O = registered_ram_do;
`else
assign WB_ACK_O = temp_ack;
assign WB_DAT_O = ram_do;
`endif
assign WB_DAT_O = ram_do;
 
 
// Generic synchronous single-port RAM interface
generic_spram #(8, 32) ram (
// Generic synchronous single-port RAM interface
444,7 → 428,7
TxEn_needed <=#Tp 1'b0;
end
 
 
reg [3:0] stm_status;
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
457,6 → 441,7
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
stm_status <=#Tp 4'h0;
end
else
begin
464,6 → 449,7
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
stm_status <=#Tp 4'h1;
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
472,6 → 458,7
end
5'b100_01 :
begin
stm_status <=#Tp 4'h2;
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
480,6 → 467,7
end
5'b010_00, 5'b010_10 :
begin
stm_status <=#Tp 4'h3;
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
490,6 → 478,7
end
5'b010_01, 5'b010_11 :
begin
stm_status <=#Tp 4'h4;
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
498,6 → 487,7
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
stm_status <=#Tp 4'h5;
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
508,10 → 498,12
end
5'b100_00 :
begin
stm_status <=#Tp 4'h6;
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
stm_status <=#Tp 4'h7;
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
/trunk/rtl/verilog/eth_top.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.24 2002/04/22 14:15:42 mohor
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
// selected in eth_defines.v
//
// Revision 1.23 2002/03/25 13:33:53 mohor
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
// name was incorrect.
373,9 → 377,9
end
else
begin
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o;
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
639,7 → 643,7
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
 
.Reset(wb_rst_i),
.Reset(r_Rst),
 
`ifdef EXTERNAL_DMA
.WB_REQ_O(wb_req_o), .WB_ND_O(wb_nd_o), .WB_RD_O(wb_rd_o),

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