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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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  • This comparison shows the changes necessary to convert path
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    from Rev 116 to Rev 117
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Rev 116 → Rev 117

/trunk/bench/verilog/tb_ethernet.v
41,10 → 41,14
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/19 13:57:53 mohor
// Testing environment also includes traffic cop, memory interface and host
// interface.
//
//
//
//
//
 
 
 
224,9 → 228,9
// forever #2.5 wb_clk_o = ~wb_clk_o; // 2*2.5 ns -> 200.0 MHz
// forever #5 wb_clk_o = ~wb_clk_o; // 2*5 ns -> 100.0 MHz
// forever #10 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 50.0 MHz
// forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
// forever #15 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 33.3 MHz
forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
// forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
// forever #25 wb_clk_o = ~wb_clk_o; // 2*25 ns -> 20.0 MHz
// forever #31.25 wb_clk_o = ~wb_clk_o; // 2*31.25 ns -> 16.0 MHz
// forever #50 wb_clk_o = ~wb_clk_o; // 2*50 ns -> 10.0 MHz
245,8 → 249,8
initial
begin
mrx_clk=0;
#16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
// #16 forever #200 mrx_clk = ~mrx_clk; // 2*200 ns -> 2.5 MHz
// #16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
#16 forever #200 mrx_clk = ~mrx_clk; // 2*200 ns -> 2.5 MHz
end
 
reg [31:0] tmp;

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